ZUSBOPTSC01ZACG datasheet(140/282 Pages) ZILOG

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PS022827-1212

P R E L I M I N A R Y Infrared Encoder/Decoder Control Register

Z8 Encore! XP® F082A Series

Product Specification

123

The window remains open until the count again reaches 8 (that is, 24 baud clock periods

since the previous pulse was detected), giving the Endec a sampling window of minus four

baud rate clocks to plus eight baud rate clocks around the expected time of an incoming

pulse. If an incoming pulse is detected inside this window this process is repeated. If the

incoming data is a logical 1 (no pulse), the Endec returns to the initial state and waits for

the next falling edge. As each falling edge is detected, the Endec clock counter is reset,

resynchronizing the Endec to the incoming signal, allowing the Endec to tolerate jitter and

baud rate errors in the incoming datastream. Resynchronizing the Endec does not alter the

operation of the UART, which ultimately receives the data. The UART is only synchro-

nized to the incoming data stream when a Start bit is received.

Infrared Encoder/Decoder Control Register Definitions

All infrared endec configuration and status information is set by the UART Control regis-

ters as defined in the Universal Asynchronous Receiver/Transmitter section on page 99.

To prevent spurious signals during IrDA data transmission, set the IREN bit in the UART

Control 1 Register to 1 to enable the Infrared Encoder/Decoder before enabling the GPIO

Port alternate function for the corresponding pin.

Caution:

ZUSBOPTSC01ZACG 数据表(PDF) 140 Page - Zilog, Inc.