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WM8944BECS/R 数据表(PDF) 123 Page - Cirrus Logic

部件名 WM8944BECS/R
功能描述  Mono Low-Power CODEC with Video Buffer
PDF  165 Pages
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制造商  CIRRUS [Cirrus Logic]
网页  http://www.cirrus.com
标志 CIRRUS - Cirrus Logic

WM8944BECS/R 数据表(HTML) 123 Page - Cirrus Logic

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WM8944B
Rev 4.3
123
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
2:1
BEEP_RATE
[1:0]
01
Beep Waveform Control
00 = Reserved
01 = 1kHz
10 = 2kHz
11 = 4kHz
0
BEEP_ENA
0
Digital Beep Enable
0 = Disabled
1 = Enabled
Note that the DAC and associated signal path needs to be
enabled when using the digital beep.
Register 25h Beep Control 1
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
R38 (26h)
Video Buffer
7
VB_ENA
0
Video buffer enable
0 = Disabled
1 = Enabled
6
VB_QBOOST
0
Video buffer filter Q-Boost control
0 = Disabled
1 = Enabled
5
VB_GAIN
0
Video buffer gain
0 = 0dB (=6dB unloaded)
1 = 6dB (=12dB unloaded)
4:2
VB_DISOFF
[2:0]
111
Video buffer DC offset control
000 = Reserved
001 = 40mV offset
010 = Reserved
011 = 20mV offset
100 = Reserved
101 = Reserved
110 = Reserved
111 = 0mV offset
Note - the specified offset applies to the 0dB gain setting
(VB_GAIN=0). When 6dB gain is selected, the DC offset is
doubled.
1
VB_PD
0
Video buffer pull-down
0 = pull-down disabled
1 = pull-down enabled
0
VB_CLAMP
0
Enable the clamp between the video input and ground
0 = no clamp
1 = Video buffer input is clamped to ground
Register 26h Video Buffer
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
R39 (27h)
Input ctrl
9
AUX_TO_N_
INPGA
0
Input PGA Inverting Input Select
0 = Connected to VMID
1 = Connected to AUX



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