STR720 datasheet(258/401 Pages) STMICROELECTRONICS

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STR720 - CONTROLLER AREA NETWORK (CAN)

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each time quantum. The rest of the CAN protocol controller, the BSP state machine is

evaluated once each bit time, at the Sample Point.

The Shift Register sends the messages serially and receives the messages parallely. Its

loading and shifting is controlled by the BSP.

The BSP translates messages into frames and vice versa. It generates and discards the

enclosing fixed format bits, inserts and extracts stuff bits, calculates and checks the CRC

code, performs the error management, and decides which type of synchronization is to be

used. It is evaluated at the Sample Point and processes the sampled bus input bit. The time

that is needed to calculate the next bit to be sent after the Sample point(e.g. data bit, CRC bit,

stuff bit, error flag, or idle) is called the Information Processing Time (IPT).

The IPT is application specific but may not be longer than 2 tq; the IPT for the CAN Peripheral

is 0 tq. Its length is the lower limit of the programmed length of Phase_Seg2. In case of a

synchronization, Phase_Seg2 may be shortened to a value less than IPT, which does not

affect bus timing.

18.7.10.6 Calculating Bit Timing Parameters

Usually, the calculation of the bit timing configuration starts with a desired bit rate or bit time.

The resulting bit time (1/bit rate) must be an integer multiple of the system clock period.

The bit time may consist of 4 to 25 time quanta, the length of the time quantum tq is defined by

the Baud Rate Prescaler with tq = (Baud Rate Prescaler)/fsys. Several combinations may lead

to the desired bit time, allowing iterations of the following steps.

First part of the bit time to be defined is the Prop_Seg. Its length depends on the delay times

measured in the system. A maximum bus length as well as a maximum node delay has to be

defined for expandible CAN bus systems. The resulting time for Prop_Seg is converted into

time quanta (rounded up to the nearest integer multiple of tq).

The Sync_Seg is 1 tq long (fixed), leaving (bit time – Prop_Seg – 1) tq for the two Phase Buffer

Segments. If the number of remaining tq is even, the Phase Buffer Segments have the same

length, Phase_Seg2

= Phase_Seg1, else Phase_Seg2 = Phase_Seg1 + 1.

The minimum nominal length of Phase_Seg2 has to be regarded as well. Phase_Seg2 may

not be shorter than the IPT of the CAN controller, which, depending on the actual

implementation, is in the range of [0..2] tq.

The length of the Synchronization Jump Width is set to its maximum value, which is the

minimum of 4 and Phase_Seg1.

The oscillator tolerance range necessary for the resulting configuration is calculated by the

formulas given in Section 18.7.10.4: Oscillator Tolerance Range on page 256

If more than one configuration is possible, that configuration allowing the highest oscillator

tolerance range should be chosen.

STR720 数据表(PDF) 258 Page - STMicroelectronics

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