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STR720 数据表(PDF) 260 Page - STMicroelectronics |
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STR720 数据表(HTML) 260 Page - STMicroelectronics |
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260 / 401 page ![]() STR720 - CONTROLLER AREA NETWORK (CAN) 260/401 In this example, the concatenated bit time parameters are (2-1)3&(7-1)4&(1-1)2&(1-1)6, the Bit Timing Register is programmed to= 0x1600. Example for Bit Timing at Low Baudrate In this example, the frequency of APB_CLK is 2 MHz, BRP is 1, the bit rate is 100 KBit/s. In this example, the concatenated bit time parameters are (4-1)3&(5-1)4&(4-1)2&(2-1)6, the Bit Timing Register is programmed to= 0x34C1. tq 1 µs= 2 •t APB_CLK delay of bus driver 200 ns delay of receiver circuit 80 ns delay of bus line (40m) 220 ns tProp 1 µs= 1 • t q tSJW 4 µs= 4 • t q tTSeg1 5 µs= t Prop + tSJW tTSeg2 4 µs = Information Processing Time + 3 • tq tSync-Seg 1 µs= 1 • t q bit time 10 µs= t Sync-Seg + tTSeg1 + tTSeg2 tolerance for APB_CLK 1.58 % = = min PB1 PB2 , () 2x 13x bit time PB2 – () () --------------------------------------------------------------- 4µs 2x 13x 10 µs 4µs – () () ---------------------------------------------------------- 1 |
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