STR720 datasheet(364/401 Pages) STMICROELECTRONICS

364 / 401 page

STR720 - POWER REDUCTION MODES

364/401

25 POWER REDUCTION MODES

The device contains a centralized clock management block (RCCU) that provides the

controlling software with a means to dynamically disable/enable the clocks to all the major

blocks in the design. The power consumption of the device may thus be tailored to the

required mode of operation.

STR720 operating modes are completely under software control via the proper configuration

of the RCCU registers. This chapter describes each of them in detail.

25.1 RUN Mode

In this operating mode STR720 can be used at its maximum performance level, since main

system clock can be programmed to reach the highest recommended frequency, either using

directly CLK input or using the on-chip PLL. In the case in which on-chip PLL is used, the

following constraints must be taken into account.

In the first place it must be considered that the range of frequencies in which PLL is able to

lock goes from 9 MHz to 27 MHz. When CLK input is driven with a signal whose frequency is

above 27 MHz, DIV2 multiplexer must be always enabled for the on-chip PLL to operate

correctly.

Besides this, another constraint comes from the maximum limit of the internal PLL VCO

frequency, which is required to be less than 1080 MHz. The value of VCO oscillation

frequency depends on the multiplication/division factors set in RCCU configuration registers

(M and D respectively) and the frequency of reference clock (CLK or CLK divided by 2 if DIV2

is enabled). The following formulas describe this relationship.

Depending on PLL configuration. the possible system frequencies generated in RUN mode

can be summarized by the following table, calculated for a generic 16 MHz clock signal

supplied to CLK input. In composing the table, PLL configuration leading to the smaller

current consumption have been chosen.

Table 82. RUN mode system frequencies (CLK=16 MHz)

PLL Multiplier / Divider

AHB / S-APB

[MHz]

A-APB min

(f/16)

A-APB max

(f/2)

ATAPI

PLL_OFF/BYP

16.00

1.00

8.00

PLL_BYP

16.00

1.00

8.00

10 / 4

40.00

2.50

20.00

21 / 8

42.00

2.63

21.00

11 / 4

44.00

2.75

22.00

23 / 8

46.00

2.88

23.00

...

VCO

2 f

REF

⋅⋅

OUT

VCO

2 D

⋅

-----------

STR720 数据表(PDF) 364 Page - STMicroelectronics

STR720 数据表(HTML) 364 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载