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数据搜索系统，热门电子元器件搜索 |
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STR720 数据表(PDF) 361 Page - STMicroelectronics |
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STR720 数据表(HTML) 361 Page - STMicroelectronics |
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361 / 401 page  STR720 - MISCELLANEA REGISTERS (GCR - CGC - AHB_ERR) 361/401 AHB Error Mask (AERR_M) Address: 0xF000_3004 Reset value: 0x0000_0000 This register allows application software to mask the FIQ interrupt generation upon the detection of any AHB error, when such feature is not required. The block will still detect faulty transfers on the system bus, just the interrupt generation is disabled. This register is read-write. Bits 31:1 = Reserved. These bits must be always written to 0. Bit 0 = AE_M: AHB Error Mask 0: AHB error interrupts masked. 1: AHB error interrupts enabled. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved - 15 14 13 12 11 10 9 8 765432 1 0 Reserved AE_M -rw |
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