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STR720 数据表(PDF) 358 Page - STMicroelectronics |
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STR720 数据表(HTML) 358 Page - STMicroelectronics |
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358 / 401 page ![]() STR720 - MISCELLANEA REGISTERS (GCR - CGC - AHB_ERR) 358/401 CGC Peripheral Under Reset register 2 (CGC-PUR2) Address: 0xF000_2C10 Reset value: 0x0000 This register configures the reset line status for each of the peripheral kernels requiring a dedicated clock. Each peripheral can be used only when its corresponding reset line is not active. Bit 15:2 = Reserved. These bits must be always written to 0. Bit 1 = D1UR: Dedicated peripheral 1 Under Reset 0: Peripheral 1 is under reset. 1: Peripheral 1 is operating normally. Bit 0 = Reserved. This bit must be always written to 0. The following table lists the correspondence between each controlled peripheral and the CGC-PUR2 register bits along with their reset value. 15 14 13 12 11 10 9 8 765432 1 0 Reserved D1UR Res. -rw - Table 78. CGC-PUR2 bit assignment CGC-PUR2 Bit Affected peripheral Reset status D1UR ATAPI-Kernel Under reset |
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