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STR720 数据表(PDF) 355 Page - STMicroelectronics |
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STR720 数据表(HTML) 355 Page - STMicroelectronics |
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355 / 401 page  STR720 - MISCELLANEA REGISTERS (GCR - CGC - AHB_ERR) 355/401 CGC Peripheral Under Reset register 1 (CGC-PUR1) Address: 0xF000_2C04 Reset value: 0x0023 This register configures the reset line status for each of the controlled AHB/S-APB peripherals. Each peripheral can be used only when its corresponding reset line is not active. Bits 15:12, 9:8, 4 = Reserved. These bits must be always written to 0. Bits 11:10, 7:5, 3:0 = PxUR: Peripheral x Under Reset 0: Peripheral x is under reset. 1: Peripheral x is operating normally. The following table lists the correspondence between each controllable peripheral and the CGC-PUR1 register bits along with their reset value. 15 14 13 12 11 10 9 8 765432 1 0 Reserved P11UR P10UR Reserved P7UR P6UR P5UR REs. P3UR P2UR P1UR P0UR - rw rw - rw rw rw - rw rw rw rw Table 75. CGC-PUR1 bit assignment CGC-PUR1 Bit Affected peripheral Reset status P0UR EMI Operative P1UR DRAMC Operative P2UR DMAC Under reset P3UR ATAPI Under reset P5UR EIC Operative P6UR GPIO-P3 Under reset P7UR GPIO-P4 Under reset P10UR WIU Under reset P11UR RTC Under reset |
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