STR720 datasheet(351/401 Pages) STMICROELECTRONICS

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STR720 - MISCELLANEA REGISTERS (GCR - CGC - AHB_ERR)

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24 MISCELLANEA REGISTERS (GCR - CGC - AHB_ERR)

24.1 Introduction

This section collects the registers setting all the aspects of STR720 which can be configured

by software. Hereafter the specification of A-GCR, S-GCR and CGC blocks can be found,

allowing application software to select between different functional options, to check the

status of relevant internal configuration signals and to control clock and reset lines of most of

internal peripherals. At the end of this section, the specification of the AHB error detection

block is reported.

24.2 A-GCR Block description

This block contains the configuration settings related to the peripherals connected to the

A-APB subsystem.

A-APB Global Configuration Register 1 (AGCR1)

Address: 0xE000_1000

Reset value: 0x0000

Bit 15:3 = Reserved. These bits must be always written to 0.

Bit 2 = ADC_STOP: ADC STOP mode

This bit can temporarily stop sampling operation of the Analog to Digital Converter block

without affecting the programming of its configuration registers.

0: ADC is operating normally.

1: ADC operations are stopped.

Bit 1 = Reserved. This bit must be always written to 0.

Bit 0 = ADC_OFF: ADC analog section OFF

This bit controls the activation of the whole analog section contained in the ADC module,

where also internal current references used for clock pad are generated. When this bit is set

to ‘1’ all the analog circuitry in the ADC module is switched off.

0: ADC analog section is switched on.

1: ADC analog section is switched off.

Note

Be careful on setting ADC_OFF bit since it switches off the current references used

by clock pad and in this condition no clock signal can be supplied to the device

through CLK pad. If this configuration is required for extreme power reduction

purposes, STR720 must be put in SLOW mode before setting ADC_OFF bit,

otherwise the system will stop responding up to the next hardware reset event.

765432

Reserved

ADC_

STOP

Res.

ADC_

OFF

-rw

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