STR720 datasheet(354/401 Pages) STMICROELECTRONICS

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STR720 - MISCELLANEA REGISTERS (GCR - CGC - AHB_ERR)

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24.4 CGC Block description

The CGC block enables to configure the AHB and S-APB peripheral clock and reset lines so

as to individually control each of them. The specific clock signals used by IDE and USB can

be controlled using dedicated registers implemented in these cell. A set 16-bit registers is

used to keep the clock gating and reset line state configuration for each of the controlled

peripherals.

CGC Peripheral Clock Gating register 1 (CGC-PCG1)

Address: 0xF000_2C00

Reset value: 0x0023

This register configures clock gating for each of the controlled AHB/S-APB peripherals. Each

peripheral can be used only when its corresponding gating bit is cleared.

Bits 15:12, 9:8, 4 = Reserved. These bits must be always written to 0.

Bits 11:10, 7:5, 3:0 = PxCO: Peripheral x Clock Off

0: Peripheral x clock is gated off and the block is not clocked.

1: Peripheral x is clocked.

The following table lists the correspondence between each controllable peripheral and the

CGC-PCG1 register bits along with their reset value.

765432

Reserved

P11CO P10CO

Reserved

P7CO

P6CO

P5CO

Res.

P3CO

P2CO

P1CO

P0CO

Table 74. CGC-PCG1 bit assignment

CGC-PCG1

Bit

Affected

peripheral

Reset

status

P0CO

EMI

P1CO

DRAMC

P2CO

DMAC

Off

P3CO

ATAPI

Off

P5CO

EIC

P6CO

GPIO-P3

Off

P7CO

GPIO-P4

Off

P10CO

WIU

Off

P11CO

RTC

Off

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