STR720 datasheet(352/401 Pages) STMICROELECTRONICS

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STR720 - MISCELLANEA REGISTERS (GCR - CGC - AHB_ERR)

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24.3 S-GCR Block description

This block contains the configuration settings related to the peripherals connected to the

S-APB subsystem and to the whole device.

S-APB Global Configuration Register 1 (SGCR1)

Address: 0xF000_0C00

Reset value: 0x0000

This register collects all software controllable configuration bits.

Bit 15:6 = Reserved. These bits must be always written to 0.

Bit 5 = CACHE_CONF: CACHE CONFiguration selection

This bit can configure SDRAM interface to work in “burst-access” mode and must be used

whenever cache is enabled, so to have optimal performance from the system.

0: Normal access mode, to be used when ARM720T cache is disabled.

1: Burst-access mode, to be used when ARM720T cache is enabled.

Note

For further details and limitation of “burst-access” mode usage see Section 10.5:

Programming considerations on page 114, in DRAM controller chapter.

Bit 4:3 = Reserved. These bits must be always written to 0.

Bit 2 = EIC_SRES: EIC Soft RESet

This bit triggers a synchronous reset of the internal sequential logic of Enhanced Interrupt

Controller, leaving priority registers unaffected. It can be useful to recover some tricky

situations occurring inside the EIC state machines without requiring full reconfiguration of EIC

registers (see Section 7.6: Application note on page 67).

0: EIC is operating normally.

1: EIC logic is kept under synchronous reset.

Bit 1 = P7AS: Port7 Access Selection

This bit selects which interface is using port 7 pins which can be shared between EMI and

IDE, for example to access external FLASH banks during system boot and then switch to

CD-ROM access to complete system start-up.

0: EMI interface uses port 7 pins.

1: IDE interface uses port 7 pins.

Bit 0 = BRM: Boot ReMap

This bit selects which memory area is mapped in the address range from 0x0000_0000 to

0x1FFF_FFFF (Block 0) and it is used to conclude the boot phase when internal RAM has

been loaded with its required contents

0: Reserved ROM or EMI area is mapped on Block 0 (see EXT_BOOT bit in SGCR2 register).

1: PROG_RAM area is mapped on Block 0.

765432

Reserved

CACHE

_CONF

Reserved

EIC_

SRES

P7AS

BRM

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