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STR720 数据表(PDF) 399 Page - STMicroelectronics |
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STR720 数据表(HTML) 399 Page - STMicroelectronics |
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399 / 401 page  STR720 - ELECTRICAL CHARACTERISTICS 399/401 The next two figures represent the write access timing, here considered in the single write case since burst write is performed using the same timing characteristics, and the entry in self-refresh (power-save) mode where MICKEN signal is used. Figure 87. SDRAM Single Write Access delay RAS-CAS latency CAS MICLK MIA[13:11] Bank MIA[10:0] Row Col MCS[x] MISA / RAS MIAA / CAS MID[32:0] Data MIWE delay precharge Activate Bank Write Precharge Bank Note: this diagram shows the timing with RAS-CAS delay, CAS latency and precharge delay all set to 1 wait-state. MIBLS[3:0] Value (output) tSCDA tSCBL |
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