DRA821U4...ALM datasheet(171/252 Pages) TI

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7.9.5.9.2.2 GPMC and NOR Flash Switching Characteristics – Asynchronous Mode

NO.

PARAMETER

DESCRIPTION

MODE

(15)

MIN

MAX

UNIT

133 MHz

FA0

tw(be[x]nV)

Pulse duration, output lower-byte enable and

command latch enable GPMC_BE0n_CLE, output

upper-byte enable GPMC_BE1n valid time

Read

(12)

Write

(12)

FA1

tw(csnV)

Pulse duration, output chip select GPMC_CSn[i](13)

low

Read

(1)

Write

(1)

FA3

td(csnV-advnIV)

Delay time, output chip select GPMC_CSn[i](13)

valid to output address valid and address latch

enable GPMC_ADVn_ALE invalid

Read

-2+B

(2)

2+B

(2)

Write

-2+B

(2)

2+B

(2)

FA4

td(csnV-oenIV)

Delay time, output chip select GPMC_CSn[i](13)

valid to output enable GPMC_OEn_REn invalid

(Single read)

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

-2+C

(3)

2+C

(3)

FA9

td(aV-csnV)

Delay time, output address GPMC_A[27:1] valid to

output chip select GPMC_CSn[i](13) valid

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

-2+J

(9)

2+J

(9)

FA10 td(be[x]nV-csnV)

Delay time, output lower-byte enable and

command latch enable GPMC_BE0n_CLE, output

upper-byte enable GPMC_BE1n valid to output

chip select GPMC_CSn[i](13) valid

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

-2+J

(9)

2+J

(9)

FA12 td(csnV-advnV)

Delay time, output chip select GPMC_CSn[i](13)

valid to output address valid and address latch

enable GPMC_ADVn_ALE valid

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

-2+K

(10)

2+K

(10)

FA13 td(csnV-oenV)

Delay time, output chip select GPMC_CSn[i](13)

valid to output enable GPMC_OEn_REn valid

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

-2+L

(11)

2+L

(11)

FA16 tw(aIV)

Pulse duration output address GPMC_A[26:1]

invalid between 2 successive read and write

accesses

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

(7)

FA18 td(csnV-oenIV)

Delay time, output chip select GPMC_CSn[i](13)

valid to output enable GPMC_OEn_REn invalid

(Burst read)

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

-2+I

(8)

2+I

(8)

FA20 tw(aV)

Pulse duration, output address GPMC_A[27:1]

valid - 2nd, 3rd, and 4th accesses

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

(4)

FA25 td(csnV-wenV)

Delay time, output chip select GPMC_CSn[i](13)

valid to output write enable GPMC_WEn valid

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

-2+E

(5)

2+E

(5)

FA27 td(csnV-wenIV)

Delay time, output chip select GPMC_CSn[i](13)

valid to output write enable GPMC_WEn invalid

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

-2+F

(6)

2+F

(6)

FA28 td(wenV-dV)

Delay time, output write enable GPMC_WEn valid

to output data GPMC_AD[15:0] valid

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

FA29 td(dV-csnV)

Delay time, output data GPMC_AD[15:0] valid to

output chip select GPMC_CSn[i](13) valid

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

-2+J

(9)

2+J

(9)

FA37 td(oenV-aIV)

Delay time, output enable GPMC_OEn_REn valid

to output address GPMC_AD[15:0] phase end

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

(1)

For single read: A = (CSRdOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)

For single write: A = (CSWrOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)

For burst read: A = (CSRdOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)

For burst write: A = (CSWrOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)

with n being the page burst access number

(2)

For reading: B = ((ADVRdOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - CSExtraDelay)) ×

GPMC_FCLK(14)

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DRA821U-Q1

SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022

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