DRA821U4...ALM datasheet(174/252 Pages) TI

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GPMC_FCLK

GPMC_CLK

GPMC_CSn[i]

GPMC_A[MSB:1]

GPMC_BE0n_CLE

GPMC_BE1n

GPMC_ADVn_ALE

GPMC_OEn_REn

GPMC_AD[15:0]

GPMC_WAIT[j]

Add0

Add1

Add2

Add3

Add4

FA1

FA0

FA18

FA13

FA12

FA0

FA9

FA10

FA21

FA20

GPMC_08

In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0 or 1.

FA21 parameter illustrates amount of time required to internally sample first input page data. It is expressed in number of GPMC

functional clock cycles. From start of read cycle and after FA21 functional clock cycles, first input page data will be internally sampled by

active functional clock edge. FA21 calculation must be stored inside AccessTime register bits field.

FA20 parameter illustrates amount of time required to internally sample successive input page data. It is expressed in number of GPMC

functional clock cycles. After each access to input page data, next input page data will be internally sampled by active functional clock

edge after FA20 functional clock cycles. FA20 is also the duration of address phases for successive input page data (excluding first

input page data). FA20 value must be stored in PageBurstAccessTime register bits field.

GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.

Figure 7-64. GPMC and NOR Flash — Asynchronous Read — Page Mode 4x16–Bit

DRA821U-Q1

SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022

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