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DRA821U4...ALM 数据表(PDF) 173 Page - Texas Instruments

部件名 DRA821U4...ALM
功能描述  DRA821 Jacinto™ Processors
PDF  252 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

DRA821U4...ALM 数据表(HTML) 173 Page - Texas Instruments

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C.
GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
Figure 7-62. GPMC and NOR Flash — Asynchronous Read — Single Word
GPMC_FCLK
GPMC_CLK
GPMC_CSn[i]
GPMC_A[MSB:1]
GPMC_BE0n_CLE
GPMC_BE1n
GPMC_ADCn_ALE
GPMC_OEn_REn
GPMC_AD[15:0]
GPMC_WAIT[j]
Address 0
Address 1
Valid
Valid
Valid
Valid
Data Upper
FA9
FA10
FA3
FA9
FA3
FA13
FA13
FA1
FA1
FA4
FA4
FA12
FA12
FA10
FA0
FA0
FA16
FA0
FA0
FA10
FA10
FA5
FA5
GPMC_07
A.
In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0 or 1.
B.
FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock
cycles. From start of read cycle and after FA5 functional clock cycles, input data will be internally sampled by active functional clock
edge. FA5 value must be stored inside AccessTime register bits field.
C.
GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
Figure 7-63. GPMC and NOR Flash — Asynchronous Read — 32–Bit
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DRA821U-Q1
SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022
Copyright © 2022 Texas Instruments Incorporated
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