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DRA821U4...ALM 数据表(PDF) 178 Page - Texas Instruments

部件名 DRA821U4...ALM
功能描述  DRA821 Jacinto™ Processors
PDF  252 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

DRA821U4...ALM 数据表(HTML) 178 Page - Texas Instruments

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7.9.5.9.3 GPMC and NAND Flash — Asynchronous Mode
Section 7.9.5.9.3.1 and Section 7.9.5.9.3.2 assume testing over the recommended operating conditions and
electrical characteristic conditions below (see Figure 7-68 through Figure 7-71).
For more information, see General-Purpose Memory Controller (GPMC) section in Peripherals chapter in the
device TRM.
7.9.5.9.3.1 GPMC and NAND Flash Timing Requirements – Asynchronous Mode
NO.
PARAMETER
DESCRIPTION
MODE
(4)
MIN
MAX
UNIT
133 MHz
GNF12
(1)
tacc(d)
Access time, input data GPMC_AD[15:0]
(3)
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
J
(2)
ns
(1)
The GNF12 parameter illustrates the amount of time required to internally sample input data. It is expressed in number of GPMC
functional clock cycles. From start of the read cycle and after GNF12 functional clock cycles, input data is internally sampled by the
active functional clock edge. The GNF12 value must be stored inside AccessTime register bit field.
(2)
J = AccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(3)
(3)
GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.
(4)
For div_by_1_mode:
GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h:
GPMC_CLK frequency = GPMC_FCLK frequency
For GPMC_FCLK_MUX:
CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 00 = CPSWHSDIV_CLKOUT3 = 2000/15 = 133.33 MHz
For TIMEPARAGRANULARITY_X1:
GPMC_CONFIG1_i Register: TIMEPARAGRANULARITY = 0h = x1 latencies (affecting RD/WRCYCLETIME, RD/
WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME,
OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE,
WRDATAONADMUXBUS)
7.9.5.9.3.2 GPMC and NAND Flash Switching Characteristics – Asynchronous Mode
NO.
PARAMETER
MODE
(15)
MIN
MAX UNIT
GNF0 tw(wenV)
Pulse duration, output write enable GPMC_WEn
valid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
A
(1)
ns
GNF1 td(csnV-wenV)
Delay time, output chip select GPMC_CSn[i](13)
valid to output write enable GPMC_WEn valid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
-2+B
(2)
2+B
(2)
ns
GNF2 tw(cleH-wenV)
Delay time, output lower-byte enable and
command latch enable GPMC_BE0n_CLE high to
output write enable GPMC_WEn valid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
-2+C
(3)
2+C
(3)
ns
GNF3 tw(wenV-dV)
Delay time, output data GPMC_AD[15:0] valid to
output write enable GPMC_WEn valid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
-2+D
(4)
2+D
(4)
ns
GNF4 tw(wenIV-dIV)
Delay time, output write enable GPMC_WEn
invalid to output data GPMC_AD[15:0] invalid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
-2+E
(5)
2+E
(5)
ns
GNF5 tw(wenIV-cleIV)
Delay time, output write enable GPMC_WEn
invalid to output lower-byte enable and command
latch enable GPMC_BE0n_CLE invalid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
-2+F
(6)
2+F
(6)
ns
GNF6 tw(wenIV-CSn[i]V) Delay time, output write enable GPMC_WEn
invalid to output chip select GPMC_CSn[i](13)
invalid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
-2+G
(7)
2+G
(7)
ns
GNF7 tw(aleH-wenV)
Delay time, output address valid and address latch
enable GPMC_ADVn_ALE high to output write
enable GPMC_WEn valid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
-2+C
(3)
2+C
(3)
ns
DRA821U-Q1
SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022
www.ti.com
178
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