DRA821U4...ALM datasheet(181/252 Pages) TI

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GPMC_CSn[i]

GPMC_BE0n_CLE

GPMC_ADVn_ALE

GPMC_OEn_REn

GPMC_FCLK

GPMC_WAIT[j]

GNF10

GNF14

GNF15

GNF12

GNF13

DATA

GPMC_AD[15:0]

GPMC_14

GNF12 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional

clock cycles. From start of read cycle and after GNF12 functional clock cycles, input data will be internally sampled by active functional

clock edge. GNF12 value must be stored inside AccessTime register bits field.

GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.

In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0 or 1.

Figure 7-70. GPMC and NAND Flash — Data Read Cycle

GPMC_FCLK

GPMC_CSn[i]

GPMC_BE0n_CLE

GPMC_ADVn_ALE

GPMC_OEn_REn

GPMC_WEn

DATA

GNF0

GNF1

GNF4

GNF9

GNF3

GNF6

GPMC_AD[15:0]

GPMC_15

In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.

Figure 7-71. GPMC and NAND Flash — Data Write Cycle

7.9.5.10 HyperBus

For more details about features and additional description information on the device HyperBus, see the

corresponding sections within Section 6.3, Signal Descriptions and Section 8, Detailed Description.

Section 7.9.5.10.1, Section 7.9.5.10.2, and Section 7.9.5.10.3 assume testing over the recommended operating

conditions and electrical characteristic conditions (see Figure 7-72, Figure 7-73, and Figure 7-74).

Table 7-40 represents HyperBus timing conditions.

Table 7-40. HyperBus Timing Conditions

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

Input Conditions

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DRA821U-Q1

SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022

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