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DRA821U4...ALM 数据表(PDF) 185 Page - Texas Instruments |
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DRA821U4...ALM 数据表(HTML) 185 Page - Texas Instruments |
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185 / 252 page  Table 7-42. I3C Open Drain Timing Parameters NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT D1 tLOW_OD Low Period of SCL Clock Controller 200 ns tDIG_OD_L tLOW_OD MIN + tFDA_OD MIN ns D2 tHIGH High Period of SCL Clock Controller 41 ns tDIG_H tHIGH + tCF ns D3 tfDA_OD Fall Time of SDA Signal Controller, Target tCF 12 ns D4 tSU_OD SDA Data Setup Time During Open Drain Mode Controller, Target 3 ns D5 tCAS Clock After START (S) Condition Controller, ENTAS0 38.4 1000 ns Controller, ENTAS1 38.4 100000 ns Controller, ENTAS2 38.4 2000000 ns Controller, ENTAS3 38.4 50000000 ns D6 tCBP Clock Before STOP (P) Condition Controller tCAS MIN / 2 ns D7 tMMOVERLAP Current Controller to Secondary Controller Overlap time during handoff Controller tDIG_OD_L min ns D8 tAVAL Bus Available Condition Controller 1000 ns D9 tIDLE Bus Idle Condition Controller 1000000 ns D10 tMMLOCK Time Internal Where New Controller Not Driving SDA Low Controller tAVALmin ns 1. This is approximately equal to tLOWmin + tDS_ODmin + trDA_ODtyp + tSU_Odmin. 2. The Controller may use a shorter Low period if the Controller knows that this is safe, when SDA is already above VIH. 3. Based on tSPIKE, rise and fall times, and interconnect. 4. This maximum High period may be exceeded when the signals can be safely seen by Legacy I2C Devices, and/or in consideration of the interconnect (for example: a short Bus). 5. On a Legacy Bus where I2C Devices need to see Start, the tCAS Min value is further constrained. 6. Targets that do not support the optional ENTASx CCCs shall use the tCAS Max value shown for ENTAS3. 7. On a Mixed Bus with Fm Legacy I2C Devices, tAVAL is 300ns shorter than the Fm Bus Free Condition time (tBUF). - Open drain with weak pull-up - Open drain with weak pull-up I3C_TIMING_01 SCL SDA D2 D1 D3 D6 Start Stop Repeated Start Stop 0.7xVDD 0.3xVDD 0.7xVDD 0.3xVDD D4 D5 Figure 7-75. I3C Open Drain Timing Table 7-43. I3C Push-Pull Timing Parameters for SDR and HDR-DDR Modes NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT D1 fSCL SCL Clock Period Controller 80 100000 ns www.ti.com DRA821U-Q1 SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 185 Product Folder Links: DRA821U-Q1 |
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