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DRA821U4...ALM 数据表(PDF) 188 Page - Texas Instruments |
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DRA821U4...ALM 数据表(HTML) 188 Page - Texas Instruments |
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188 / 252 page  NO.1 PARAMETER DESCRIPTION MODE MIN MAX UNIT ASP6 th(ACLKRX-AFSRX) Hold time, AFSR/X input valid after ACLKR/X ACLKR/X int -1 ns ACLKR/X ext in/out 1.6 ASP7 tsu(AXR-ACLKRX) Setup time, AXR input valid before ACLKR/X ACLKR/X int 12.3 ns ACLKR/X ext in/out 4 ASP8 th(ACLKRX-AXR) Hold time, AXR input valid after ACLKR/X ACLKR/X int -1 ns ACLKR/X ext in/out 1.6 1. ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1 ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0 ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1 ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1 ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0 ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1 2. P = AHCLKR/X period in ns. 3. R = ACLKR/X period in ns. ASP8 ASP7 ASP4 ASP4 ASP3 ASP2 ASP2 ASP1 A0 A1 B0 B1 A30 A31 B30 B31 C0 C1 C2 C3 C31 MCASP[x]_ACLKR/X (Falling Edge Polarity) MCASP[x]_AHCLKR/X (Rising Edge Polarity) MCASP[x]_AFSR/X (Bit Width, 0 Bit Delay) MCASP[x]_AFSR/X (Bit Width, 1 Bit Delay) MCASP[x]_AFSR/X (Bit Width, 2 Bit Delay) MCASP[x]_AFSR/X (Slot Width, 0 Bit Delay) MCASP[x]_AFSR/X (Slot Width, 1 Bit Delay) MCASP[x]_AFSR/X (Slot Width, 2 Bit Delay) MCASP[x]_AXR[x] (Data In/Receive) ASP6 ASP5 MCASP[x]_ACLKR/X (CLKRP = CLKXP = 0) (A) MCASP[x]_ACLKR/X (CLKRP = CLKXP = 1) (B) A. For CLKRP = CLKXP = 0, the MCASP transmitter is configured for rising edge (to shift data out) and the MCASP receiver is configured for falling edge (to shift data in). B. For CLKRP = CLKXP = 1, the MCASP transmitter is configured for falling edge (to shift data out) and the MCASP receiver is configured for rising edge (to shift data in). Figure 7-77. MCASP Input Timing DRA821U-Q1 SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022 www.ti.com 188 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DRA821U-Q1 |
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