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DRA821U4...ALM 数据表(PDF) 190 Page - Texas Instruments

部件名 DRA821U4...ALM
功能描述  DRA821 Jacinto™ Processors
PDF  252 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

DRA821U4...ALM 数据表(HTML) 190 Page - Texas Instruments

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Table 7-47 and Figure 7-78 present switching characteristics over recommended operating conditions for
MCASP0 to MCASP11.
Table 7-47. Switching Characteristics Over Recommended Operating Conditions for MCASP
NO.1
PARAMETER
DESCRIPTION
MODE
MIN
MAX
UNIT
ASP9 tc(AHCLKRX)
Cycle time, AHCLKR/X
20
ns
ASP10 tw(AHCLKRX)
Pulse duration, AHCLKR/X high or low
-2 + 0.5P2
ns
ASP11 tc(ACLKRX)
Cycle time, ACLKR/X
20
ns
ASP12 tw(ACLKRX)
Pulse duration, ACLKR/X high or low
-2 + 0.5R3
ns
ASP13 td(ACLKRX-AFSRX) Delay time, ACLKR/X transmit edge to AFSR/X
output valid
ACLKR/X int
0
7.25
ns
ACLKR/X ext in/out
-15.28
12.84
ASP14 td(ACLKX-AXR)
Delay time, ACLKX transmit edge to AXR output valid ACLKR/X int
0
7.25
ns
ACLKR/X ext in/out
-15.28
12.84
ASP15 tdis(ACLKX-AXR)
Disable time, ACLKX transmit edge to AXR output
high impedance
ACLKR/X int
0
7.25
ns
ACLKR/X ext in/out
-14.9
14
1. ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1
ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0
ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1
ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1
2. P = AHCLKR/X period in ns.
3. R = ACLKR/X period in ns.
DRA821U-Q1
SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022
www.ti.com
190
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Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: DRA821U-Q1



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