DRA821U4...ALM datasheet(192/252 Pages) TI

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Table 7-48. MCSPI Timing Conditions

PARAMETER

MIN

MAX

UNIT

Input Conditions

SRI

Input slew rate

8.5

V/ns

Output Conditions

Output load capacitance

CLK

D[x], CSi

7.9.5.15.1 MCSPI — Controller Mode

Table 7-49, Figure 7-79, Table 7-50, and Figure 7-80 present timing requirements and switching characteristics

for MCSPI – Controller Mode.

Table 7-49. MCSPI Timing Requirements - Controller Mode

see Figure 7-79

PARAMETER

MIN

MAX

UNIT

SM4

tsu(misoV-

spiclkV)

Setup time, SPI_D[x] valid before SPI_CLK active edge

2.9

SM5

th(spiclkV-

misoV)

Hold time, SPI_D[x] valid after SPI_CLK active edge

Table 7-50. MCSPI Switching Characteristics - Controller Mode

see Figure 7-80

PARAMETER

MODE

MIN

MAX

UNIT

SM1

tc(spiclk)

Cycle time, SPI_CLK

20.8

SM2

tw(spiclkL)

Pulse duration, SPI_CLK low

0.5P -

1(1)

SM3

tw(spiclkH)

Pulse duration, SPI_CLK high

0.5P -

1(1)

SM6

td(spiclkV-simoV)

Delay time, SPI_CLK active edge to SPI_D[x]

transition

–2

SM7

td(csV-simoV)

Delay time, SPI_CSi active edge to SPI_D[x] transition

SM8

td(csV-spiclk)

Delay time, SPI_CSi active to SPI_CLK first edge

PHA = 0(2)

B - 4(3)

PHA = 1 (2)

A - 4(4)

SM9

td(spiclkV-csV)

Delay time, SPI_CLK last edge to SPI_CSi inactive

PHA = 0(2)

A - 4(4)

PHA = 1(2)

B - 4(3)

(1)

P = SPI_CLK period in ns

(2)

SPI_CLK phase is programmable with the PHA bit of the MCSPI_CHCONF_0/1/2/3 register

(3)

B = (TCS + .5) * TSPICLKREF, where TCSns a bit field of the MCSPI_CHCONF_0/1/2/3 register and Fratio = Even >= 2.

(4)

When P = 20.8 ns, A = (TCS + 1) * TSPICLKREF, where TCSns a bit field of the MCSPI_CHCONF_0/1/2/3 register.

When P > 20.8 ns, A = (TCS + 0.5) * Fratio * TSPICLKREF, where TCSns a bit field of the MCSPI_CHCONF_0/1/2/3 register.

DRA821U-Q1

SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022

www.ti.com

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