DRA821U4...ALM datasheet(195/252 Pages) TI

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7.9.5.15.2 MCSPI — Peripheral Mode

Table 7-51, Figure 7-81, Table 7-52, and Figure 7-82 present timing requirements and switching characteristics

for MCSPI – Peripheral Mode.

Table 7-51. MCSPI Timing Requirements - Peripheral Mode

PARAMETER

MIN

MAX

UNIT

SS1

tc(spiclk)

Cycle time, SPI_CLK

20.8

SS2

tw(spiclkL)

Pulse duration, SPI_CLK low

0.45P(1)

SS3

tw(spiclkH)

Pulse duration, SPI_CLK high

0.45P(1)

SS4

tsu(simoV-spiclkV)

Setup time, SPI_D[x] valid before SPI_CLK active edge

SS5

th(spiclkV-simoV)

Hold time, SPI_D[x] valid after SPI_CLK active edge

SS8

tsu(csV-spiclkV)

Setup time, SPI_CSi valid before SPI_CLK first edge

SS9

th(spiclkV-csV)

Hold time, SPI_CSi valid after SPI_CLK last edge

Table 7-52. MCSPI Switching Characteristics - Peripheral Mode

PARAMETER

MIN

MAX

UNIT

SS6

td(spiclkV-

somiV)

Delay time, SPI_CLK active edge to SPI_D[x] transition

17.12

SS7

tsk(csV-somiV) Delay time, SPI_CSi active edge to SPI_D[x] transition

20.95

(1)

P = SPI_CLK period in ns.

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DRA821U-Q1

SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022

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