DRA821U4...ALM datasheet(197/252 Pages) TI

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SPI_CS[i]

(IN)

SPI_SCLK

(IN)

SPI_SCLK

(IN)

SPI_D[x]

(OUT)

SPI_CS[i]

(IN)

SPI_SCLK

(IN)

SPI_SCLK

(IN)

SPI_D[x]

(OUT)

Bit n-1

Bit n-2

Bit n-3

Bit n-4

Bit 0

Bit n-1

Bit n-2

Bit n-3

Bit 1

Bit 0

PHA=0

EPOL=1

POL=0

POL=1

POL=0

POL=1

PHA=1

EPOL=1

SS6

SS3

SS1

SS3

SS1

SS3

SS1

SS2

SS1

SS6

SS8

SS9

SS7

SS8

SS2

SS3

SS2

SS6

SS9

SPRSP08_TIMING_McSPI_03

Figure 7-82. MCSPI Peripheral Mode Transmit Timing

For more information, see Multichannel Serial Peripheral Interface (MCSPI) section in Peripherals chapter in the

device TRM.

7.9.5.16 eMMC/SD/SDIO

The MMCSD Host Controller provides an interface to eMMC 5.1 (embedded MultiMedia Card), SD 4.10 (Secure

Digital), and SDIO 4.0 (Secure Digital IO) devices. The MMCSD Host Controller deals with MMC/SD/SDIO

protocol at transmission level, data packing, adding cyclic redundancy checks (CRCs), start/end bit insertion,

and checking for syntactical correctness.

For more details about features and additional description information on the device Multi Media Card, see the

corresponding sections within Section 6.3, Signal Descriptions and Section 8, Detailed Description.

Note

MMC modes require software configuration of the delay settings, as shown in Table 7-53 and Table

7-63.

Tuning algorithm should be implemented to meet input setup/hold time requirements for SDR50,

DDR50 (only on MMCSD1), SDR104, HS200 and HS400 modes.

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DRA821U-Q1

SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022

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