DRA821U4...ALM datasheet(200/252 Pages) TI

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Figure 7-85. MMCSD0 – High Speed SDR Mode – Receive Mode

Table 7-58. MMCSD0 Switching Characteristics - High Speed SDR Mode

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

fop(clk)

Operating frequency, MMC0_CLK

MHz

HSSDR5

tc(clk)

Cycle time, MMC0_CLK

HSSDR6

tw(clkH)

Pulse duration, MMC0_CLK high

9.2

HSSDR7

tw(clkL)

Pulse duration, MMC0_CLK low

9.2

HSSDR8

td(clkL-cmdV)

Delay time, MMC0_CLK falling edge to MMC0_CMD transition

–3.2

3.8

HSSDR9

td(clkL-dV)

Delay time, MMC0_CLK falling edge to MMC0_DAT[7:0] transition

–3.2

3.8

Figure 7-86. MMCSD0 – High Speed SDR Mode – Transmit Mode

7.9.5.16.1.3 High Speed DDR Mode

Table 7-59 and Table 7-60 present Timing requirements and Switching characteristics for MMCSD0 – High

Speed DDR Mode (see Figure 7-87 and Figure 7-88).

Table 7-59. MMCSD0 Timing Requirements - High Speed DDR Mode

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

HSDDR1 tsu(cmdV-clkH)

Setup time, MMC0_CMD valid before MMC0_CLK rising edge

2.5

HSDDR2 th(clkH-cmdV)

Hold time, MMC0_CMD valid after MMC0_CLK rising edge

2.67

HSDDR3 tsu(dV-clkV)

Setup time, MMC0_DAT[7:0] valid before MMC0_CLK transition

0.83

HSDDR4 th(clkV-dV)

Hold time, MMC0_DAT[7:0] valid after MMC0_CLK transition

1.76

Figure 7-87. MMCSD0 – High Speed DDR Mode – Receive Mode

DRA821U-Q1

SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022

www.ti.com

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