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DRA821U4...ALM 数据表(PDF) 203 Page - Texas Instruments |
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DRA821U4...ALM 数据表(HTML) 203 Page - Texas Instruments |
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203 / 252 page  7.9.5.16.2 MMCSDi — MMCSD1 — SD/SDIO Interface Note The MMCSDi (i = 1) controller is also referred to as MMCi. MMCSDi interface is compliant with the SD Host Controller Standard Specification 4.10 and SD Physical Layer Specification v3.01 as well as SDIO Specification v3.00 and it supports the following SD Card applications: • Default speed • High speed • UHS–I SDR12 • UHS–I SDR25 • UHS–I SDR50 • UHS–I SDR104 • UHS–I DDR50 Table 7-63 presents the required delay software configuration settings for MMC1 timing modes. Table 7-63. MMC1 Delay Mapping for All Timing Modes REGISTER NAME MMCSD12_SS_PHY_CTRL_4_REG MMCSD12_SS_PHY_CTRL_5_REG BIT FIELD [20] [15:12] [8] [4:0] [2:0] BIT FIELD NAME OTAPDLYENA OTAPDLYSEL ITAPDLYENA ITAPDLYSEL CLKBUFSEL MODE DESCRIPTION DELAY ENABLE DELAY VALUE INPUT DELAY ENABLE INPUT DELAY VALUE DELAY BUFFER DURATION Default Speed 4-bit PHY operating 3.3 V, 25 MHz 0x1 0x0 0x0 0x0 0x7 High Speed 4-bit PHY operating 3.3 V, 50 MHz 0x1 0x0 0x0 0x0 0x7 UHS-I SDR12 4-bit PHY operating 1.8 V, 25 MHz 0x1 0xF 0x0 0x0 0x7 UHS-I SDR25 4-bit PHY operating 1.8 V, 50 MHz 0x1 0xF 0x0 0x0 0x7 UHS-I SDR50 4-bit PHY operating 1.8 V, 100 MHz 0x1 0xC 0x1 Tuning 0x7 UHS-I DDR50 4-bit PHY operating 1.8 V, 50 MHz 0x1 0xC 0x1 Tuning 0x7 UHS-I SDR104 4-bit PHY operating 1.8, V 200 MHz 0x1 0x5 0x1 Tuning 0x7 Table 7-64 represents MMCSD1 timing conditions. Table 7-64. MMCSD1 Timing Conditions PARAMETER DESCRIPTION MODE MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate Default Speed, High Speed 0.69 2.06 V/ns UHS-I SDR12, UHS-I SDR25 0.34 1.34 V/ns UHS-I DDR50 1 2 V/ns OUTPUT CONDITIONS CL Output load capacitance All Speed Modes 1 10 pF PCB CONNECTIVITY REQUIREMENTS www.ti.com DRA821U-Q1 SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 203 Product Folder Links: DRA821U-Q1 |
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