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DRA821U4...ALM 数据表(PDF) 204 Page - Texas Instruments |
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DRA821U4...ALM 数据表(HTML) 204 Page - Texas Instruments |
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204 / 252 page  Table 7-64. MMCSD1 Timing Conditions (continued) PARAMETER DESCRIPTION MODE MIN MAX UNIT td(Trace Delay) Propagation delay of each trace Default Speed, High Speed 126 1200 ps UHS-I DDR50 255 1134 ps All Other Modes 134 1276 ps td(Trace Mismatch Delay) Propagation delay mismatch across all traces UHS-I DDR50 20 ps UHS-I SDR104 8 ps All Other Modes 100 ps 7.9.5.16.2.1 Default speed Mode Table 7-65 and Table 7-66 present timing requirements and switching characteristics for MMCSDi – Default Speed Mode (see Figure 7-91 and Figure 7-92) Table 7-65. MMCSD1 Timing Requirements – Default Speed Mode NO. PARAMETER DESCRIPTION MIN MAX UNIT DS1 tsu(cmdV-clkH) Setup time, MMC[x]_CMD valid before MMC[x]_CLK rising edge 2.15 ns DS2 th(clkH-cmdV) Hold time, MMC[x]_CMD valid after MMC[x]_CLK rising edge 4.56 ns DS3 tsu(dV-clkH) Setup time, MMC[x]_DAT[3:0] valid before MMC[x]_CLK rising edge 2.15 ns DS4 th(clkH-dV) Hold time, MMC[x]_DAT[3:0] valid after MMC[x]_CLK rising edge 4.56 ns 1. x = 1 for MMC1 MMC[ ]_CLK x M [ ]_ MC CMD x MMC DAT [ ]_ [3:0] x DS1 DS2 DS3 DS4 Figure 7-91. MMCSD1 – Default Speed – Receive Mode Table 7-66. MMCSD1 Switching Characteristics – Default Speed Mode NO. PARAMETER DESCRIPTION MIN MAX UNIT fop(clk) Operating frequency, MMC[x]_CLK 25 MHz DS5 tc(clk) Cycle time, MMC[x]_CLK 40 ns DS6 tw(clkH) Pulse duration, MMC[x]_CLK high 18.7 ns DS7 tw(clkL) Pulse duration, MMC[x]_CLK low 18.7 ns DS8 td(clkL-cmdV) Delay time, MMC[x]_CLK falling edge to MMC[x]_CMD transition –3.53 3.53 ns DS9 td(clkL-dV) Delay time, MMC[x]_CLK falling edge to MMC[x]_DAT[3:0] transition –3.53 3.53 ns MMC[ ]_CLK x MMC CMD [ ]_ x MMC DAT [ _ [3:0] x] D 5 S D 7 S D 8 S D 9 S DS6 Figure 7-92. MMCSD1 – Default Speed – Transmit Mode DRA821U-Q1 SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022 www.ti.com 204 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DRA821U-Q1 |
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