| 数据搜索系统,热门电子元器件搜索 |
|
DRA821U4...ALM 数据表(PDF) 205 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
DRA821U4...ALM 数据表(HTML) 205 Page - Texas Instruments |
|
205 / 252 page ![]() 7.9.5.16.2.2 High Speed Mode Table 7-67 and Table 7-68 present timing requirements and switching characteristics for MMCSDi – High Speed Mode (see Figure 7-93 and Figure 7-94). Table 7-67. MMCSD1 Timing Requirements – High Speed Mode NO. PARAMETER DESCRIPTION MIN MAX UNIT HS1 tsu(cmdV-clkH) Setup time, MMC[x]_CMD valid before MMC[x]_CLK rising edge 2.15 ns HS2 th(clkH-cmdV) Hold time, MMC[x]_CMD valid after MMC[x]_CLK rising edge 2.26 ns HS3 tsu(dV-clkH) Setup time, MMC[x]_DAT[3:0] valid before MMC[x]_CLK rising edge 2.15 ns HS4 th(clkH-dV) Hold time, MMC[x]_DAT[3:0] valid after MMC[x]_CLK rising edge 2.26 ns MMC[ ]_CLK x MMC[ ]_CMD x MMC DAT [ ]_ [3:0] x H 1 S H 2 S H 3 S H 4 S Figure 7-93. MMCSD1 – High Speed – Receive Mode Table 7-68. MMCSD1 Switching Characteristics – High Speed Mode NO. PARAMETER DESCRIPTION MIN MAX UNIT fop(clk) Operating frequency, MMC[x]_CLK 50 MHz HS5 tc(clk) Cycle time. MMC[x]_CLK 20 ns HS6 tw(clkH) Pulse duration, MMC[x]_CLK high 9.2 ns HS7 tw(clkL) Pulse duration, MMC[x]_CLK low 9.2 ns HS8 td(clkL-cmdV) Delay time, MMC[x]_CLK falling edge to MMC[x]_CMD transition –2.07 2.07 ns HS9 td(clkL-dV) Delay time, MMC[x]_CLK falling edge to MMC[x]_DAT[3:0] transition –2.07 2.07 ns MMC[x]_CLK MMC CMD [ ]_ x MMC DAT [ ]_ [3:0] x H 5 S H 7 S H 8 S H 9 S HS6 Figure 7-94. MMCSD1 – High Speed – Transmit Mode 7.9.5.16.2.3 UHS–I SDR12 Mode Table 7-69 and Table 7-70 present timing requirements and switching characteristics for MMCSDi – UHS-I SDR12 Mode(see Figure 7-95 and Figure 7-96). Table 7-69. MMCSD1 Timing Requirements – UHS-I SDR12 Mode NO. PARAMETER DESCRIPTION MIN MAX UNIT SDR121 tsu(cmdV-clkH) Setup time, MMC[x]_CMD valid before MMC[x]_CLK rising edge 5.46 ns SDR122 th(clkH-cmdV) Hold time, MMC[x]_CMD valid after MMC[x]_CLK rising edge 1.67 ns SDR123 tsu(dV-clkH) Setup time, MMC[x]_DAT[3:0] valid before MMC[x]_CLK rising edge 5.46 ns www.ti.com DRA821U-Q1 SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 205 Product Folder Links: DRA821U-Q1 |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |