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DRA821U4...ALM 数据表(PDF) 209 Page - Texas Instruments |
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DRA821U4...ALM 数据表(HTML) 209 Page - Texas Instruments |
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209 / 252 page  7.9.5.16.2.7 UHS–I SDR104 Mode Table 7-75 presents timing requirements and switching characteristics for MMCSDi – UHS-I SDR104 Mode (see Figure 7-101) Table 7-75. MMCSD1 Switching Characteristics – UHS-I SDR104 Mode NO. PARAMETER DESCRIPTION MIN MAX UNIT fop(clk) Operating frequency, MMC[x]_CLK 200 MHz SDR1045 tc(clk) Cycle time, MMC[x]_CLK 5 ns SDR1046 tw(clkH) Pulse duration, MMC[x]_CLK high 2.12 ns SDR1047 tw(clkL) Pulse duration, MMC[x]_CLK low 2.12 ns SDR1048 td(clkH-cmdV) Delay time, MMC[x]_CLK rising edge to MMC[x]_CMD transition 2.12 3.2 ns SDR1049 td(clkH-dV) Delay time, MMC[x]_CLK rising edge to MMC[x]_DAT[3:0] transition 2.12 3.2 ns MMC[ ]_CLK x MMC CMD [ ]_ x MMC DAT [ ]_ [3:0] x SDR1045 SDR1047 SDR1046 SDR1048 SDR1049 SDR1048 SDR1049 Figure 7-101. MMCSD1 – UHS-I SDR104 – Transmit Mode 7.9.5.17 NAVSS Table 7-76 represents CPTS timing conditions. Table 7-76. CPTS Timing Conditions PARAMETER DESCRIPTION MIN MAX UNIT Input Conditions tSR Input slew rate 0.5 5 V/ns Output Conditions CLOAD Output load capacitance 2 10 pF Section 7.9.5.17.1, Section 7.9.5.17.2, Figure 7-102, and Figure 7-103 present timing requirement and switching characteristics of the CPTS interface. 7.9.5.17.1 Timing Requirements for CPTS Input NO. PARAMETER DESCRIPTION MIN MAX UNIT T1 tw(HWn_TS_PUSHH) HWn_TS_PUSH Pulse duration, high 2.1 + 12P (1) ns T2 tw(HWn_TS_PUSHL) HWn_TS_PUSH pulse duration, low 2.1 + 12P (1) ns T3 tc(RFT_CLK) RFT_CLK cycle time 5 8 ns T4 tw(RFT_CLKH) RFT_CLK pulse duration, high 0.45 × tc(RFT_CLK) ns T5 tw(RFT_CLKL) RFT_CLK pulse duration, low 0.45 × tc(RFT_CLK) ns (1) P = functional clock period in ns. www.ti.com DRA821U-Q1 SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 209 Product Folder Links: DRA821U-Q1 |
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