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DRA821U4...ALM 数据表(PDF) 211 Page - Texas Instruments |
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DRA821U4...ALM 数据表(HTML) 211 Page - Texas Instruments |
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211 / 252 page  Table 7-77. OSPIx Timing Conditions (continued) PARAMETER MODE MIN MAX UNIT SRI Input slew rate 1 6 V/ns OUTPUT CONDITIONS CL Output load capacitance 3 10 pF PCB CONNECTIVITY REQUIREMENTS td(Trace Delay) Propagation delay of OSPI0_CLK traces No Loopback Internal PHY Loopback Internal Pad Loopback 450 ps Propagation delay of OSPI0_LBCLKO traces External Board Loopback 2L(1) - 30 2L(1) + 30 ps Propagation delay of OSPI0_DQS traces DQS L(1) - 30 L(1) + 30 ps td(Trace Mismatch Delay) Propagation delay mismatch of OSPIx_D[7:0] and OSPIx_CSn[3:0] relative to OSPIx_CLK All modes 60 ps (1) L = Propagation delay of OSPIx_CLK trace For more information, see Octal Serial Peripheral Interface (OSPI) section in Peripherals chapter in the device TRM. 7.9.5.18.1 OSPI With Data Training 7.9.5.18.1.1 OSPI Switching Characteristics – Data Training PARAMETER DESCRIPTION MODE MIN MAX UNIT tc(CLK) Cycle time, CLK DDR, 1.8V 6.02 ns DDR, 3.3V 7.52 ns tc(CLK) Cycle time, CLK SDR, 1.8V 6.02 ns SDR, 3.3V 7.52 ns 7.9.5.18.2 OSPI Without Data Training Note The I/O Timings provided in this section are only applicable when data training is not implemented. Additionally, the I/O Timings are valid only for some OSPI usage modes when the corresponding DLL Delays are configured as described in Table 7-78 found in this section. Section 7.9.5.18.2.1, Section 7.9.5.18.2.2, Figure 7-104, and Figure 7-105 present switching characteristics for OSPI DDR and SDR Mode. 7.9.5.18.2.1 OSPI Switching Characteristics – DDR Mode NO.(1) PARAMETER DESCRIPTION MODE MIN MAX UNIT O1 tc(CLK) Cycle time, CLK 1.8V 19 ns 3.3V 19 ns O2 tw(CLKL) Pulse duration, CLK low -0.3+0.475*P (2) ns O3 tw(CLKH) Pulse duration, CLK high -0.3+0.475*P (2) ns O4 td(CLK-CSn) Delay time, CSn[3:0] active edge to CLK rising edge 1.8V, OSPI0 DDR TX; 1.8V, OSPI1 DDR TX -7-0.475 * P – 0.975 * N * R (3) (4) (5) 0.525 * P + 1.025 * M * R + 1 (3) (4) (5) ns 3.3V, OSPI0 DDR TX; 3.3V, OSPI1 DDR TX -7-0.475 * P – 0.975 * N * R (3) (4) (5) 0.525 * P + 1.025 * M * R + 1 (3) (4) (5) ns www.ti.com DRA821U-Q1 SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 211 Product Folder Links: DRA821U-Q1 |
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