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(3)

P = SCLK period

(4)

M = OSPI_DEV_DELAY_REG[D_INIT_FLD], N = OSPI_DEV_DELAY_REG[D_AFTER_FLD]

(5)

R = refclk

OSPI_CLK

OSPI_TIMING_02

OSPI_CSn

O10

O11

O12

OSPI_D[i:0]

Figure 7-105. OSPI Switching Characteristics – SDR

Section 7.9.5.18.2.3, Section 7.9.5.18.2.4, Figure 7-106, Figure 7-107, Figure 7-108, and Figure 7-109 presents

timing requirements for OSPI DDR and SDR Mode.

7.9.5.18.2.3 OSPI Timing Requirements – DDR Mode

NO.

(1)

PARAMETER

DESCRIPTION

MODE

MIN

MAX

UNIT

O13 tsu(D-CLK)

Setup time, D[i:0] valid before active CLK edge

1.8V, No Loopback Clock; 1.8V,

Internal Pad Loopback Clock

5.23

3.3V, No Loopback Clock; 3.3V,

Internal Pad Loopback Clock

6.19

O14 th(CLK-D)

Hold time, D[i:0] valid after active CLK edge

1.8V, No Loopback Clock; 1.8V,

Internal Pad Loopback Clock

1.84

3.3V, No Loopback Clock; 3.3V,

Internal Pad Loopback Clock

2.34

O15 tsu(D-LBCLK)

Setup time, D[i:0] valid before active LBCLK (DQS)

edge

1.8V, External Board Loopback

Clock

0.52

3.3V, External Board Loopback

Clock

1.97

O16 th(LBCLK-D)

Hold time, D[i:0] valid after active LBCLK (DQS)

edge

1.8V, External Board Loopback

Clock

1.2 (2)

3.3V, External Board Loopback

Clock

1.44 (2)

O17 tsu(D-DQS)

Setup time, DQS edge to D[i:0] transition

1.8V, OSPI0 DQS;

1.8V, OSPI1 DQS

-0.46

3.3V, OSPI0 DQS;

3.3V, OSPI1 DQS

-0.66

O18 th(DQS-D)

Hold time, DQS edge to D[i:0] transition

1.8V, OSPI0 DQS;

1.8V, OSPI1 DQS

3.59

3.3V, OSPI0 DQS;

3.3V, OSPI1 DQS

7.92

(1)

i in [i:0] = 7 for OSPI0, i in [i:0] = 3 for OSPI1

(2)

This Hold time requirement is larger than the Hold time provided by a typical flash device. Therefore, the trace length between the SoC

and flash device must be sufficiently long enough to ensure that the Hold time is met at the SoC. The length of the SoC's external

loopback clock (OSPI_LBCLKO to OSPI_DQS) may need to be shortened to compensate.

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DRA821U-Q1

SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022

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