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DRA821U4...ALM 数据表(PDF) 216 Page - Texas Instruments |
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DRA821U4...ALM 数据表(HTML) 216 Page - Texas Instruments |
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216 / 252 page  NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT T4 tw(TOUTL) Pulse duration, low PWM -2.5 + 4P (1) ns (1) P = functional clock period in ns. T1 T2 TIMER_IOx (inputs) TIMER_01 T3 T4 TIMER_IOx (outputs) Figure 7-110. Timer Timing For more information, see Timers section in Peripherals chapter in the device TRM. 7.9.5.21 UART For more details about features and additional description information on the device Universal Asynchronous Receiver Transmitter, see the corresponding sections within Section 6.3, Signal Descriptions and Section 8, Detailed Description. Table 7-80 represents UART timing conditions. Table 7-80. UART Timing Conditions PARAMETER DESCRIPTION MIN MAX UNIT Input Conditions tSR Input slew rate 0.5 5 V/ns Output Conditions CLOAD Output load capacitance 1 30(1) pF (1) This value represents an absolute maximum load capacitance. As the UART baud rate increases, it may be necessary to reduce the load capacitance to a value less than this maximum limit to provide enough timing margin for the attached device. The output rise/fall times increase as capacitive load increases, which decreases the time data is valid for the receiver of the attached devices. Therefore, it is important to understand the minimum data valid time required by the attached device at the operating baud rate. Then use the device IBIS models to verify the actual load capacitance on the UART signals does not increase the rise/fall times beyond the point where the minimum data valid time of the attached device is violated. Section 7.9.5.21.1, Section 7.9.5.21.2, and Figure 7-111 present timing requirements and switching characteristics for UART interface. 7.9.5.21.1 UART Timing Requirements NO. PARAMETER DESCRIPTION MIN MAX UNIT 4 tw(RX) Pulse width, receive data bit, high or low 0.95U(1) (2) 1.05U(1) (2) ns 5 tw(CTS) Pulse width, receive start bit, high or low 0.95U(1) (2) ns (1) U = UART baud time = 1/Programmed baud rate (2) This value defines the data valid time, where the input voltage is required to be above VIH or below VIL. 7.9.5.21.2 UART Switching Characteristics NO. PARAMETER DESCRIPTION MIN MAX UNIT f(baud) Maximum programmable baud rate 12 Mbps 2 tw(TX) Pulse width, transmit data bit, high or low U - 2(1) U + 2(1) ns DRA821U-Q1 SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022 www.ti.com 216 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DRA821U-Q1 |
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