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DRA821U4...ALM 数据表(PDF) 214 Page - Texas Instruments |
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DRA821U4...ALM 数据表(HTML) 214 Page - Texas Instruments |
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214 / 252 page  OSPI_CLK O14 O13 OSPI_TIMING_03 OSPI_D[i:0] O14 O13 Figure 7-106. OSPI Timing Requirements – DDR, No Loopback Clock and Internal Pad Loopback Clock OSPI_DQS O16 O15 OSPI_TIMING_04 OSPI_D[i:0] O16 O15 Figure 7-107. OSPI Timing Requirements – DDR, External Loopback Clock and DQS 7.9.5.18.2.4 OSPI Timing Requirements – SDR Mode NO. (1) PARAMETE R DESCRIPTION MODE MIN MAX UNIT O19 tsu(D-CLK) Setup time, D[i:0] valid before active CLK edge 1.8V, No Loopback Clock 4.8 ns 3.3V, No Loopback Clock 5.39 ns O20 th(CLK-D) Hold time, D[i:0] valid after active CLK edge 1.8V, No Loopback Clock -0.5 ns 3.3V, No Loopback Clock -0.5 ns O21 tsu(D-LBCLK) Setup time, D[i:0] valid before active LBCLK input (DQS) edge 1.8V, External Board Loopback Clock 0.6 ns 3.3V, External Board Loopback Clock 0.9 ns O22 th(LBCLK-D) Hold time, D[i:0] valid after active LBCLK input (DQS) edge 1.8V, External Board Loopback Clock 1.7 ns 3.3V, External Board Loopback Clock 2 ns (1) i in [i:0] = 7 for OSPI0, i in [i:0] = 3 for OSPI1 OSPI_CLK OSPI_D[i:0] OSPI_TIMING_05 O 9 1 O20 Figure 7-108. OSPI Timing Requirements – SDR, No Loopback Clock and Internal Pad Loopback Clock OSPI_DQS OSPI_TIMING_06 O21 O 2 2 OSPI_D[i:0] Figure 7-109. OSPI Timing Requirements – SDR, External Loopback Clock DRA821U-Q1 SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022 www.ti.com 214 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DRA821U-Q1 |
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