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DRA821U4...ALM 数据表(PDF) 217 Page - Texas Instruments |
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DRA821U4...ALM 数据表(HTML) 217 Page - Texas Instruments |
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217 / 252 page  NO. PARAMETER DESCRIPTION MIN MAX UNIT 3 tw(RTS) Pulse width, transmit start bit, high or low U - 2(1) ns (1) U = UART baud time = 1/Programmed baud rate UARTi_TXD 4 Start Bit Data Bits 3 UARTi_RXD 2 Data Bits Bit Start 1 V IH V IL UART_TIMING_01_RCVRVIHVIL Figure 7-111. UART Timing For more information, see Universal Asynchronous Receiver/Transmitter (UART) section in Peripherals chapter in the device TRM. 7.9.5.22 USB The USB 2.0 subsystem is compliant with the Universal Serial Bus (USB) Specification, revision 2.0. Refer to the specification for timing details. The USB 3.1 GEN1 Dual-Role Device Subsystem is compliant with the Universal Serial Bus (USB) 3.1 Specification, revision 1.0. Refer to the specification for timing details. For more details about features and additional description information on the device Universal Serial Bus Subsystem (USB), see the corresponding sections within Section 6.3, Signal Descriptions and Section 8, Detailed Description. For more information, see Universal Serial Bus (USB) Subsystem section in Peripherals chapter in the device TRM. 7.9.6 Emulation and Debug 7.9.6.1 Debug Trace Table 7-82 represents Debug Trace timing conditions. Table 7-81. Debug Trace Timing Conditions PARAMETER MIN MAX UNIT Output Conditions CL Output load capacitance 2 5 pF PCB CONNECTIVITY REQUIREMENTS td(Trace Mismatch) Propagation delay mismatch across all traces 200 ps Table 7-82 and Figure 7-112 assume testing over the recommended operating conditions and electrical characteristic conditions. Table 7-82. Debug Trace Switching Characteristics NO. PARAMETER DESCRIPTION MIN MAX UNIT 1.8 V Mode DBTR1 tc(TRC_CLK) Cycle time, TRC_CLK 6.50 ns DBTR2 tw(TRC_CLKH) Pulse width, TRC_CLK high 2.50 ns www.ti.com DRA821U-Q1 SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 217 Product Folder Links: DRA821U-Q1 |
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