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8.2 Processor Subsystems

8.2.1 Arm Cortex-A72

The device implements one dual-core Arm® Cortex®-A72 MPU, which is integrated inside the Compute Cluster,

along with other modules. The Cortex-A72 cores are general-purpose processors that can be used for running

customer applications.

The A72SS is built around the Arm Cortex-A72 MPCore (A72 cluster), which is provided by Arm and configured

by TI. It is based on the symmetric multiprocessor (SMP) architecture, and thus it delivers high performance and

optimal power management and debug capabilities.

The A72 processor is a multi-issue out-of-order superscalar execution engine with integrated L1 instruction and

data caches, compatible with Armv8-A architecture. The Armv8-A architecture brings a number of new features.

These include 64-bit data processing, extended virtual addressing and 64-bit general purpose registers.

For more information, see Dual-A72 MPU Subsystem section in Processors and Accelerators chapter in the

device TRM.

8.2.2 Arm Cortex-R5F

The MCU_ARMSS is a dual-core implementation of the Arm® Cortex®-R5F processor configured for split/lock

operation. It also includes accompanying memories (L1 caches and tightly-coupled memories), standard Arm®

CoreSight™ debug and trace architecture, integrated Vectored Interrupt Manager (VIM), ECC Aggregators, and

various wrappers for protocol conversion and address translation for easy integration into the SoC.

For more information, see Dual-R5F MCU Subsystem section in Processors and Accelerators chapter in the

device TRM.

8.3 Other Subsystems

8.3.1 MSMC

The

Multicore

Shared

Memory

Controller

(MSMC)

forms

the

heart

the

compute

cluster

(COMPUTE_CLUSTER0) providing high-bandwidth resource access both to and from all of the connected

processing elements and the rest of the system. MSMC serves as the data-movement backbone of the compute

cluster.

For more information, see Multicore Shared Memory Controller (MSMC) section in Device Configuration chapter

in the device TRM.

8.3.2 NAVSS

8.3.2.1 NAVSS0

Main SoC Navigator Subsystem (NAVSS0) consists of DMA/Queue Management components – UDMA and

Ring Accelerator (UDMASS), Peripherals (Module subsystem [MODSS]), Virtualization translation (VirtSS), and

a North Bridge (NBSS).

8.3.2.2 MCU_NAVSS

MCU Navigator Subsystem (MCU NAVSS) has a subset of the modules of the main NAVSS and is instantiated

in the MCU domain.

MCU Navigator Subsystem consists of DMA/Queue Management components – UDMA and Ring Accelerator

(UDMASS), and Peripherals (Module subsystem [MODSS]).

For more information, see Main Navigator Subsystem (NAVSS) and MCU Navigator Subsystem (MCU NAVSS)

sections in Data Movement Architecture (DMA) chapter in the device TRM.

8.3.3 PDMA Controller

The Peripheral DMA is a simple DMA which has been architected to specifically meet the data transfer

needs of peripherals, which perform data transfers using memory mapped registers accessed via a standard

non-coherent bus fabric. The PDMA module is intended to be located close to one or more peripherals which

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DRA821U-Q1

SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022

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