DRA821U4...ALM datasheet(222/252 Pages) TI

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require an external DMA for data movement and is architected to reduce cost by using VBUSP interfaces and

supporting only statically configured Transfer Request (TR) operations.

The PDMA is only responsible for performing the data movement transactions which interact with the peripherals

themselves. Data which is read from a given peripheral is packed by a PDMA source channel into a PSI-L data

stream which is then sent to a remote peer UDMA-P destination channel which then performs the movement of

the data into memory. Likewise, a remote UDMA-P source channel fetches data from memory and transfers it to

a peer PDMA destination channel over PSI-L which then performs the writes to the peripheral.

The PDMA architecture is intentionally heterogeneous (UDMA-P + PDMA) to right size the data transfer

complexity at each point in the system to match the requirements of whatever is being transferred to or

from. Peripherals are typically FIFO based and do not require multi-dimensional transfers beyond their FIFO

dimensioning requirements, so the PDMA transfer engines are kept simple with only a few dimensions (typically

for sample size and FIFO depth), hardcoded address maps, and simple triggering capabilities.

Multiple source and destination channels are provided within the PDMA which allow multiple simultaneous

transfer operations to be ongoing. The DMA controller maintains state information for each of the channels and

employs round-robin scheduling between channels in order to share the underlying DMA hardware.

For more information, see PDMA Controller section in DMA Controllers chapter in the device TRM.

8.3.4 Peripherals

8.3.4.1 ADC

The Analog-to-Digital Converter (ADC) module contains a single 12-bit ADC which can be multiplexed to any 1

of 8 analog inputs (channels).

For more information, see Analog-to-Digital Converter (ADC) section in Peripherals chapter in the device TRM.

8.3.4.2 ATL

The Audio Tracking Logic (ATL) is used by HD Radio™ applications to synchronize the digital audio output to

the baseband clock. This same IP can also be used generically to track errors between two reference signals

(such as frame syncs) and generate a modulated clock output (using software-controlled cycle stealing) which

averages to some desired frequency. This process can be used as a hardware assist for asynchronous sample

rate conversion algorithms.

For more information, see Audio Tracking Logic (ATL) section in Peripherals chapter in the device TRM.

8.3.4.3 CPSW2G

The two-port Gigabit Ethernet MAC (MCU_CPSW0) subsystem provides Ethernet packet communication for the

device and is configured in a similar manner as an Ethernet switch. MCU_CPSW0 features the Reduced Gigabit

Media Independent Interface (RGMII), Reduced Media Independent Interface (RMII), and the Management Data

Input/Output (MDIO) interface for physical layer device (PHY) management.

For more information, see Gigabit Ethernet Switch (CPSW0) section in Peripherals chapter in the device TRM.

8.3.4.4 CPSW5G

The 5-port Gigabit Ethernet Switch (CPSW0) subsystem provides Ethernet packet communication for the

device and can be configured as an Ethernet switch. CPSW0 features the 1G and 2.5G Serial Gigabit Media

Independent Interface (SGMII), Universal Serial 10G Media Independent Interface (USXGMII), 10G Form-factor

Interface (XFI), Reduced Gigabit Media Independent Interface (RGMII), Reduced Media Independent Interface

(RMII) and the Management Data Input/Output (MDIO) interface for physical layer device (PHY) management.

For more information, see Gigabit Ethernet Switch (MCU_CPSW0) section in Peripherals chapter in the device

TRM.

8.3.4.5 DCC

The Dual Clock Comparator (DCC) is used to determine the accuracy of a clock signal during the time

execution of an application. Specifically, the DCC is designed to detect drifts from the expected clock frequency.

DRA821U-Q1

SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022

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