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parallel and can be used on any memory system. Channel 1 can also be put into data trace mode, where MCRC

controller compresses each data being read through CPU read data bus.

For more information, see MCRC Controller section in Interprocessor Communication chapter in the device

TRM.

8.3.4.20 MCSPI

The MCSPI module is a multichannel transmit/receive, master/slave synchronous serial bus.

There are total of eleven MCSPI modules in the device.

For more information, see Multichannel Serial Peripheral Interface (MCSPI) section in Peripherals chapter in the

device TRM.

8.3.4.21 MMC/SD

The MMCSD Host Controller provides an interface to eMMC 5.1 (embedded MultiMedia Card), SD 4.10 (Secure

Digital), and SDIO 4.0 (Secure Digital IO) devices. The MMCSD Host Controller deals with MMC/SD/SDIO

protocol at transmission level, data packing, adding cyclic redundancy checks (CRCs), start/end bit insertion,

and checking for syntactical correctness.

For more information, see Multimedia Card/Secure Digital (MMC/SD) Interface section in Peripherals chapter in

the device TRM.

8.3.4.22 OSPI

The Octal Serial Peripheral Interface (OSPI™) module is a kind of Serial Peripheral Interface (SPI) module

which allows single, dual, quad or octal read and write access to external flash devices.

The OSPI module is used to transfer data, either in a memory mapped direct mode (for example a processor

wishing to execute code directly from external flash memory), or in an indirect mode where the module is set-up

to silently perform some requested operation, signaling its completion via interrupts or status registers.

For more information, see Octal Serial Peripheral Interface (OSPI) section in Peripherals chapter in the device

TRM.

8.3.4.23 PCIE

The Peripheral Component Interconnect Express (PCIe) subsystem is built around a multi-lane dual-mode PCIe

controller that provides low pin-count, high reliability, and high-speed data transfers at rates of up to 8.0 Gbps

per lane for serial links on backplanes and printed wiring boards.

For more information, see Peripheral Component Interconnect Express (PCIe) Subsystem section in Peripherals

chapter in the device TRM.

8.3.4.24 SerDes

SerDes'es goal is to convert device (SoC) parallel data into serialized data that can be output over a highspeed

electrical interface. In the opposite direction, SerDes converts high-speed serial data into parallel data that can

be processed by the device. To this end, the SerDes contains a variety of functional blocks to handle both the

external analog interface as well as the internal digital logic.

For more information, see Serializer/Deserializer (SerDes) section in Peripherals chapter in the device TRM.

8.3.4.25 WWDT

The Windowed Watchdog Timer provides timer functionality for operating systems and for benchmarking code.

The module incorporates several counters, which define the timebases needed for scheduling in the operating

system. The module is implemented with an RTI module, but only WWDT is supported.

This module is specifically designed to fulfill the requirements for OSEK (“Offene Systeme und deren

Schnittstellen für die Elektronik im Kraftfahrzeug”; “Open Systems and the Corresponding Interfaces for

Automotive Electronics”) as well as OSEK/Time compliant operating systems.

For more information, see Real Time Interrupt (RTI) Module section in Peripherals chapter in the device TRM.

DRA821U-Q1

SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022

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