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DRA821U4...ALM 数据表(PDF) 228 Page - Texas Instruments |
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DRA821U4...ALM 数据表(HTML) 228 Page - Texas Instruments |
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228 / 252 page ![]() 9 Applications, Implementation, and Layout Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test design implementation to confirm system functionality. 9.1 Power Supply Mapping TPS6594x and LP8764x are the Power Management ICs (PMIC) that should be used for Power Distribution Network (PDN) designs to support this device. TI requires use of these PMICs for the following reasons: • TI has validated their use with the Device • Board level margins including transient response and output accuracy are analyzed and optimized for the entire system • Support for power sequencing requirements (refer to Section 7.9.2, Power Supply Sequences) • Support for Adaptive Voltage Scaling (AVS) Class 0 requirements, including TI provided software When combining device voltage domains into a common power rail is allowed, the most strigent voltage domain PDN guideline must be implemented for the common power rail. It is possible that some device voltage domains may be unused in some systems. In such cases, all unused voltage domain supply pins must still be connected to a valid power rail with a proper voltage level in order to ensure device reliability (refer to Section 4.3, Signal Descriptions). For example, if MCU is not used, then vdd_mcu domain can be combined with the CORE domain (vdd_core) that has the same voltage specifications. A buck converter power stage connected to the common power rail would then supply both CORE and MCU domains. For the combined rail, the following relaxations apply: • The AVS voltage of active rail in the combined rail needs to be used to set the power supply • The decoupling capacitance should be set according to the active rail in the combined rail Figure 9-1 shows an example of the detailed power mapping between the processor and TPS659414-Q1 and LP876441-Q1 PMICs. In this configuration, both PMIC devices use a 3.3V input voltage. For more details, refer to the appnote titled “User's Guide for Powering DRA821 with the TPS6594-Q1 and LP8764-Q1 PMICs". DRA821U-Q1 SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022 www.ti.com 228 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DRA821U-Q1 |
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