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jitter performance of clock, PLL and DLL signals. Combining analog VDDA_1p8_<phy> domains should be

avoided but if grouped, then in-line ferrite bead supply filtering is required.

6. VDDA_1P8_<phy> are 1.8V analog domains supporting multiple serial PHY interfaces. A low noise, analog

supply is recommended to provide best signal integrity, interface performance and spec compliance. If any of

these interfaces are not needed, data bit errors or non-compliant operation can be tolerated, then domains

can be grouped with digital IO 1.8V power rail either directly or through an in-line supply filter is allowed.

7. VDDA_0P8_<dll/pll> are 0.8V analog domains supporting PLL and DLL circuitry needing a low noise supply

for optimal performance. It is not recommended to combine these domains with any other 0.8V domains

since high frequency switching noise could negatively impact jitter performance of PLL and DLL signals.

8. VDD_MCU is a digital voltage domain with a wide range enabling it to be grouped and ramped-up with either

0.8V VDD_CORE or 0.85V RAM array (VDDAR_xxx) domains.

9.2 Device Connection and Layout Fundamentals

9.2.1 Power Supply Decoupling and Bulk Capacitors

9.2.1.1 Power Distribution Network Implementation Guidance

The Sitara Processor Power Distribution Networks: Implementation and Analysis provides guidance for

successful implementation of the power distribution network. This includes PCB stackup guidance as well as

guidance for optimizing the selection and placement of the decoupling capacitors. TI supports only designs that

follow the board design guidelines contained in the application report.

9.2.2 External Oscillator

For more information about External Oscillators, see Section 7.9.4, Clock Specifications

9.2.3 JTAG and EMU

Texas Instruments supports a variety of eXtended Development System (XDS) JTAG controllers with various

debug capabilities beyond only JTAG support. A summary of this information is available in the XDS Target

Connection Guide.

For more recommendations on EMU routing, see Emulation and Trace Headers Technical Reference Manual

9.2.4 Reset

The device incorporates four external reset pins (MCU_PORz, MCU_RESETz, PORz, and RESET_REQz) and

two reset status pins (MCU_RESETSTATz and RESETSTATz). These pins can be driven by an external power

good circuitry or Power Management IC (PMIC). MCU_PORz and Main PORz pins should be held active low

during the entire power-up phase, and until all power supplies as well as the HFOSC0 clock are stable.

All MCU domain resets act as master resets to the whole device, whereas Main domain resets only reset Main

domain (MCU domain is reset isolated from all Main domain resets).

9.2.5 Unused Pins

For more information about Unused Pins, see Section 6.5, Connections for Unused Pins

9.2.6 Hardware Design Guide for JacintoTM 7 Devices

The Hardware Design Guide for JacintoTM 7 Devices document describes hardware system design

considerations for the JacintoTM 7 family of processors.This design guide is intended to be used as an aid

during the development of application hardware.

9.3 Peripheral- and Interface-Specific Design Information

9.3.1 LPDDR4 Board Design and Layout Guidelines

The goal of the Jacinto 7 DDR Board Design and Layout Guidelines is to make the LPDDR4 system

implementation straightforward for all designers. Requirements have been distilled down to a set of layout and

routing rules that allow designers to successfully implement a robust design for the topologies that TI supports.

TI only supports board designs using LPDDR4 memories that follow the guidelines in this document.

DRA821U-Q1

SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022

www.ti.com

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