DRA821U4...ALM datasheet(233/252 Pages) TI

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9.3.2 OSPI and QSPI Board Design and Layout Guidelines

The following section details the routing guidelines that must be observed when routing the OSPI and QSPI

interfaces.

9.3.2.1 No Loopback and Internal Pad Loopback

• The MCU_OSPI[x]_CLK output signal must be connected to the CLK pin of the flash device

• The signal propagation delay from the MCU_OSPI[x]_CLK signal to the flash device must be < 450 ps (~7cm

as stripline or ~8cm as microstrip)

• 50 Ω PCB routing is recommended along with series terminations, as shown in Figure 9-2

• Propagation delays and matching:

– A to B < 450 ps

– Matching skew: < 60 ps

MCU_OSPI[x]_CLK

OSPI/QSPI/SPI

Device Clock Input

OSPI/QSPI/SPI

Device IO[y], CS#

MCU_OSPI[x]_D[y],

MCU_OSPI[x]_CSn[z]

MCU_OSPI_Board_01

MCU_OSPI[x]_LBCLKO

MCU_OSPI[x]_DQS

OSPI Device DQS

* 0 Ω resistor (R1), located as close as possible to the MCU_OSPI[x]_CLK pin, is placeholder for fine tuning, if needed.

Figure 9-2. OSPI Interface High Level Schematic

9.3.2.2 External Board Loopback

• The MCU_OSPI[x]_CLK output signal must be connected to the CLK pin of the flash device

• The MCU_OSPI[x]_LBCLKO output signal must be looped back into the MCU_OSPI[x]_DQS input

• The signal propagation delay from the MCU_OSPI[x]_CLK pin to the flash device CLK input pin (A to B)

should be approximately equal to half of the signal propagation delay from the MCU_OPSI[x]_LBCLKO pin to

the MCU_OSPI[x]_DQS pin ((C to D)/2). See the note below.

www.ti.com

DRA821U-Q1

SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022

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