DRA821U4...ALM datasheet(235/252 Pages) TI

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• The signal propagation delay from the MCU_OSPI[x]_CLK pin to the flash device CLK input pin (A to B)

should be approximately equal to the signal propagation delay from the MCU_OSPI[x]_DQS pin to the DQS

output pin (C to D)

• 50 Ω PCB routing is recommended along with series terminations, as shown in Figure 9-4

• Propagation delays and matching:

– A to B = C to D

– Matching skew: < 60 ps

MCU_OSPI[x]_CLK

OSPI/QSPI/SPI

device clock input

J7ES_OSPI_Board_03

MCU_OSPI[x]_DQS

OSPI device DQS

OSPI/QSPI/SPI

device IOy, CS#

MCU_OSPI[x]_D[y],

MCU_OSPI[x]_CSn[z]

* 0 Ω resistor (R1), located as close as possible to the MCU_OSPI[x]_CLK pin, is a placeholder for fine tuning, if needed.

Figure 9-4. OSPI Interface High Level Schematic

9.3.3 USB VBUS Design Guidelines

The USB 3.1 specification allows the VBUS voltage to be as high as 5.5 V for normal operation, and as high as

20 V when the Power Delivery addendum is supported. Some automotive applications require a max voltage to

be 30 V.

The device requires the VBUS signal voltage be scaled down using an external resistor divider (as shown in

the Figure 9-5), which limits the voltage applied to the actual device pin (USB0_VBUS). The tolerance of these

external resistors should be equal to or less than 1%, and the leakage current of zener diode at 5 V should be

less than 100 nA.(1)

www.ti.com

DRA821U-Q1

SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022

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