DRA821U4...ALM datasheet(230/252 Pages) TI

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Table 9-1. Combined MCU and Main Voltage Domain Power Rail Mapping

TYPES

VOLTAGE [V]

DOMAIN NAMES

DOMAIN TYPES

POWER RAILS

Digital IO

3.3

(VDDSHV0_MCU,

VDDSHV1_MCU,

VDDSHV2_MCU,

VDDSHV0, VDDSHV2,

VDDSHV5(3))(1),

VDDA_3P3_USB(4)

VDDSHVn_MCU,VDDSH

Vn, VDDA_3P3_USB(1)

VDD_IO_3V3

Digital IO

1.8

(VDDSHV0_MCU,

VDDSHV1_MCU,

VDDSHV2_MCU,

VDDSHV0, VDDSHV2,

VDDSHV5(3))(2) ,

VDDS_MMC0

VDDSHVn_MCU3

VDDSHVn(2), (3)

VDD_IO_1V8

Analog PHY

1.8

(VDDA_MCU_PLLGRP0,

VDDA_MCU_TEMP,

VDDA_ADC_MCU,

VDDA_POR_WKUP,

VDDA_WKUP,

VDDA_OSC1,

VDDA_PLLGRP8,6,4,0,

VDDA_TEMP1:0)(5),

VDDA_1P8_USB,

VDDA_1P8_SERDES)(6)

VDDA_1P8_<clk/

meas>(5)

VDDA_1P8_<phy>(6)

VDA_LN_1V8(6), (7)

Analog, low

voltage

0.80

(VDDA_0P8_PLL_DDR,

VDDA_0P8_DLL_MMC0

)(7)

VDDA_0P8_DPLL

VDA_DPLL_0V8

Digital, AVS low

voltage

0.77 – 0.84

VDD_CPU

VDD_CPU_AVS

Digital, low

voltage

0.80

VDD_MCU9,

VDD_MCU_WAKE1,VD

D_CORE,VDD_WAKE0,

(VDDA_0P8_SERDES,

VDDA_0P8_USB)

VDD_MCU

VDD_CORE

VDDA_0P8_<phy>

VDD_CORE_0V8

Digital, low

voltage

0.85

VDDAR_MCU,VDDAR_

CORE, VDDAR_CPU

VDDAR

VDD_RAM_0V85

Digital, low

voltage

1.1

VDDS_DDR_BIAS,

VDDS_DDR,

VDDS_DDR_C

VDDS_DDR

VDD_DDR_1V1

(1)

Any MCU or Main dual voltage IO domains (VDDSHVn_MCU or VDDSHVn) being supplied by 3.3V to support 3.3V digital interfaces

(2)

Any MCU or Main dual voltage IO domains (VDDSHVn_MCU or VDDSHVn) being supplied by 1.8V to support 1.8V digital interfaces

(3)

VDDSHV5 supports MMC1 signaling for SD memory cards. A dual voltage (3.3/1.8V) power rail is required for compliant, high-speed

SD card operations. If SD card is not needed or standard data rates with fixed 3.3V operation is acceptable, then domain can be

grouped with digital IO 3.3V power rail. If a SD card is capable of operating with fixed 1.8V, then domain can be grouped with digital IO

1.8V power rail.

(4)

VDDA_3P3_USB is 3.3V analog domain used for USB 2.0 differential interface signaling. A low noise, analog supply is recommended

to provide best signal integrity for USB data eye mask compliance. If USB interface is not needed or data bit errors can be tolerated,

then domain can be grouped with 3.3V digital IO power rail either directly or through a supply filter.

(5)

VDDA_1P8_<clk/pll/ana> are 1.8V analog domains supporting clock oscillator, PLL and analog circuitry needing a low noise supply

for optimal performance. It is not recommended to combine digital VDDSHVn_MCU and VDDSHVn IO domains since high frequency

switching noise could negatively impact jitter performance of clock, PLL and DLL signals. Combining analog VDDA_1p8_<phy>

domains should be avoided but if grouped, then in-line ferrite bead supply filtering is required.

(6)

VDDA_1P8_<phy> are 1.8V analog domains supporting multiple serial PHY interfaces. A low noise, analog supply is recommended

to provide best signal integrity, interface performance and spec compliance. If any of these interfaces are not needed, data bit errors

or non-compliant operation can be tolerated, then domains can be grouped with digital IO 1.8V power rail either directly or through an

in-line supply filter is allowed.

(7)

VDDA_0P8_<dll/pll> are 0.8V analog domains supporting PLL and DLL circuitry needing a low noise supply for optimal performance.

It is not recommended to combine these domains with any other 0.8V domains since high frequency switching noise could negatively

impact jitter performance of PLL and DLL signals.

DRA821U-Q1

SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022

www.ti.com

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