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DRA821U4...ALM 数据表(PDF) 219 Page - Texas Instruments |
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DRA821U4...ALM 数据表(HTML) 219 Page - Texas Instruments |
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219 / 252 page  Table 7-83. JTAG Timing Conditions PARAMETER MIN MAX UNIT Input Conditions tSR Input slew rate 0.50 2.00 V/ns Output Conditions CL Output load capacitance 5 15 pF PCB CONNECTIVITY REQUIREMENTS td(Trace Delay) Propagation delay of each trace 83.5 1000(1) ps td(Trace Mismatch Delay) Propagation delay mismatch across all traces 100 ps (1) Maximum propagation delay associated with the JTAG signal traces has a significant impact on maximum TCK operating frequency. It may be possible to increase the trace delay beyond this value, but the operating frequency of TCK must be reduced to account for the additional trace delay. 7.9.6.2.1 JTAG Electrical Data and Timing Section 7.9.6.2.1.1, Section 7.9.6.2.1.2, and Figure 7-113 assume testing over the recommended operating conditions and electrical characteristic conditions. 7.9.6.2.1.1 Timing Requirements for IEEE 1149.1 JTAG NO. MIN MAX UNIT J1 tc(TCK) Cycle time minimum, TCK 46.5(1) ns J2 tw(TCKH) Pulse width minimum, TCK high 0.4P(2) ns J3 tw(TCKL) Pulse width minimum, TCK low 0.4P(2) ns J4 tsu(TDI-TCK) Input setup time minimum, TDI valid to TCK high 4.5 ns tsu(TMS-TCK) Input setup time minimum, TMS valid to TCK high 4.5 ns J5 th(TCK-TDI) Input hold time minimum, TDI valid from TCK high 2 ns th(TCK-TMS) Input hold time minimum, TMS valid from TCK high 2 ns (1) The maximum TCK operating frequency assumes the following timing requirements and switching characteristics for the attached debugger. The operating frequency of TCK must be reduced to provide appropriate timing margin if the debugger exceeds any of these assumptions. • Minimum TDO setup time of 4.6 ns relative to the rising edge of TCK • TDI and TMS output delay in the range of -16.5 ns to 14.0 ns relative to the falling edge of TCK (2) P = TCK cycle time in ns 7.9.6.2.1.2 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG NO. PARAMETER DESCRIPTION MIN MAX UNIT J6 td(TCKL-TDOI) Delay time minimum, TCK low to TDO invalid 0 ns J7 td(TCKL-TDOV) Delay time maximum, TCK low to TDO valid 12 ns TDO J2 J1 J4 TCK J5 TDI / TMS J3 J6 J7 J4 J5 Figure 7-113. JTAG Test–Port Timing www.ti.com DRA821U-Q1 SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 219 Product Folder Links: DRA821U-Q1 |
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