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DRA821U4...ALM 数据表(PDF) 201 Page - Texas Instruments

部件名 DRA821U4...ALM
功能描述  DRA821 Jacinto™ Processors
PDF  252 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

DRA821U4...ALM 数据表(HTML) 201 Page - Texas Instruments

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Table 7-60. MMCSD0 Switching Characteristics - High Speed DDR Mode
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
fop(clk)
Operating frequency, MMC0_CLK
50
MHz
HSDDR5 tc(clk)
Cycle time, MMC0_CLK
20
ns
HSDDR6 tw(clkH)
Pulse duration, MMC0_CLK high
9.2
ns
HSDDR7 tw(clkL)
Pulse duration, MMC0_CLK low
9.2
ns
HSDDR8 td(clkH-cmdV)
Delay time, MMC0_CLK rising edge to MMC0_CMD transition
3.31
9.8
ns
HSDDR9 td(clkV-dV)
Delay time, MMC0_CLK transition to MMC0_DAT[7:0] transition
2.81
6.94
ns
Figure 7-88. MMCSD0 – High Speed DDR Mode – Transmit Mode
7.9.5.16.1.4 HS200 Mode
Table 7-61 presents Switching characteristics for MMCSD0 – HS200 Mode (see Figure 7-89).
Table 7-61. MMCSD0 Switching Characteristics - HS200 Mode
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
fop(clk)
Operating frequency, MMC0_CLK
200
MHz
HS2005
tc(clk)
Cycle time, MMC0_CLK
5
ns
HS2006
tw(clkH)
Pulse duration, MMC0_CLK high
2.08
ns
HS2007
tw(clkL)
Pulse duration, MMC0_CLK low
2.08
ns
HS2008
td(clkL-cmdV)
Delay time, MMC0_CLK rising edge to MMC0_CMD transition
0.99
3.28
ns
HS2009
td(clkL-dV)
Delay time, MMC0_CLK rising edge to MMC0_DAT[7:0] transition
0.99
3.28
ns
Figure 7-89. MMCSD0 – HS200 Mode – Transmit Mode
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DRA821U-Q1
SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022
Copyright © 2022 Texas Instruments Incorporated
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