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DRA821U4...ALM 数据表(PDF) 191 Page - Texas Instruments

部件名 DRA821U4...ALM
功能描述  DRA821 Jacinto™ Processors
PDF  252 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

DRA821U4...ALM 数据表(HTML) 191 Page - Texas Instruments

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ASP15
ASP14
ASP13
ASP13
ASP12
ASP12
ASP11
ASP10
ASP10
ASP9
A0
A1
B0
B1
A30 A31
B30 B31 C0
C1 C2 C3
C31
ASP13
ASP13
ASP13
ASP13
ASP13
MCASP[x]_ACLKR/X (Falling Edge Polarity)
MCASP[x]_AHCLKR/X (Rising Edge Polarity)
MCASP[x]_AFSR/X (Bit Width, 0 Bit Delay)
MCASP[x]_AFSR/X (Bit Width, 1 Bit Delay)
MCASP[x]_AFSR/X (Bit Width, 2 Bit Delay)
MCASP[x]_AFSR/X (Slot Width, 0 Bit Delay)
MCASP[x]_AFSR/X (Slot Width, 1 Bit Delay)
MCASP[x]_AFSR/X (Slot Width, 2 Bit Delay)
MCASP[x]_AXR[x] (Data Out/Transmit)
MCASP[x]_ACLKR/X (CLKRP = CLKXP = 1)
(A)
MCASP[x]_ACLKR/X (CLKRP = CLKXP = 0)
(B)
A.
For CLKRP = CLKXP = 1, the MCASP transmitter is configured for falling edge (to shift data out) and the MCASP receiver is configured
for rising edge (to shift data in).
B.
For CLKRP = CLKXP = 0, the MCASP transmitter is configured for rising edge (to shift data out) and the MCASP receiver is configured
for falling edge (to shift data in).
Figure 7-78. MCASP Output Timing
1. x in MCASP[x]_* is 0, 1 or 2
For more information, see Multichannel Audio Serial Port (MCASP) section in Peripherals chapter in the device
TRM.
7.9.5.15 MCSPI
For more details about features and additional description information on the device Serial Port Interface, see
the corresponding sections within Section 6.3, Signal Descriptions and Section 8, Detailed Description.
For more information, see Multichannel Serial Peripheral Interface (MCSPI) section in Peripherals chapter in the
device TRM.
Table 7-48 represents MCSPI timing conditions.
www.ti.com
DRA821U-Q1
SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022
Copyright © 2022 Texas Instruments Incorporated
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Product Folder Links: DRA821U-Q1



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