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DRA821U4...ALM 数据表(PDF) 186 Page - Texas Instruments

部件名 DRA821U4...ALM
功能描述  DRA821 Jacinto™ Processors
PDF  252 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

DRA821U4...ALM 数据表(HTML) 186 Page - Texas Instruments

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Table 7-43. I3C Push-Pull Timing Parameters for SDR and HDR-DDR Modes (continued)
NO.
PARAMETER
DESCRIPTION
MODE
MIN
MAX
UNIT
D2
tLOW
SCL Clock Low Period
Controller
24
ns
tDIG_L
32
ns
D3
tHIGH_MIXED
SCL Clock High Period of Mixed Bus (Mixed Bus Topology
Not Supported)
Controller
24
ns
tDIG_H_MIXED
32
45
ns
D4
tHIGH
SCL Clock High Period
Controller
24
ns
tDIG_H
32
ns
D5
tSCO
Clock in to Data Out for Target
Target
12
ns
D6
tCR
SCL Clock Rise Time
Controller
150 × 1 /
fSCL
60
ns
D7
tCF
SCL Clock Fall Time
Controller
150 × 1 /
fSCL
60
ns
D8
tHD_PP
SDA Signal Data Hold in Push Pull Mode
Controller
tCR + 3
and tCF +
3
ns
Target
0
ns
D9
tSU_PP
SDA Signal Data Setup In Push-Pull Mode
Controller,
Target
3
ns
D10
tCASr
Clock After Repeated START (Sr)
Controller
tCAS MIN
ns
D11
tCBSr
Clock Before Repeated START (Sr)
Controller
tCAS MIN /
2
ns
1. FSCL = 1 / (tDIG_L + tDIG_H)
2. tDIG_L and tDIG_H are the clock Low and High periods as seen at the receiver end of the I3C Bus using VIL
and VIH.
3. When communicating with an I3C Device on a mixed Bus, the tDIG_H_MIXED period must be constrained to
make sure that I2C Devices do not interpret I3C signaling as valid I2C signaling.
4. As both edges are used, the hold time needs to be satisfied for the respective edges; tCF + 3 for falling edge
clocks, and tCR + 3 for rising edge clocks.
5. Clock Frequency Minimum 0.01 MHz, Maximum 12.5 MHz
- Open drain with weak pull-up
- Open drain with weak pull-up
I3C_TIMING_02
SCL
SDA
D1
D2
D7
D6
D8
D9
D5
Start
Stop
Repeated
Start
Stop
0.7xVDD
0.3xVDD
0.7xVDD
0.3xVDD
D9
D5
D4
D11
D10
Figure 7-76. I3C Push-Pull Timing (SDR and HDR-DDR Modes)
DRA821U-Q1
SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022
www.ti.com
186
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Product Folder Links: DRA821U-Q1



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