DRA821U4...ALM datasheet(183/252 Pages) TI

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HYPERBUS_TIMING_01

CK, CKn

D8/LFD8

RWDS

DQ[7:0]

D9/LFD9

Command-Address

Host drives DQ[7:0] and Memory drives RWDS

CK and Data are center aligned

Host drives DQ[7:0] and RWDS

39:32

31:24

23:16

15:8

7:0

47:40

Dn+1 Dn+1

D7/LFD7

D6/LFD6

D11/LFD11

D10/LFD10

D12/LFD12

CSn

Figure 7-72. HyperBus Timing Diagrams – Transmitter Mode

HYPERBUS_TIMING_02

RWDS

DQ[7:0]

Command-Address

Host drives DQ[7:0] and Memory drives RWDS

CK and Data are center aligned

Host drives DQ[7:0] and RWDS

39:32

31:24

23:16

15:8

7:0

47:40

Dn+1 Dn+1

CK, CKn

D8/LFD8

D9/LFD9

D7/LFD7

D6/LFD6

D10/LFD10

D12/LFD12

D5/LFD5

CSn

Figure 7-73. HyperBus Timing Diagrams – Receiver Mode

RESETn

HYPERBUS_TIMING_03

CSn

Figure 7-74. HyperBus Timing Diagrams – Reset

For more information, see HyperBus Interface section in Peripherals chapter in the device TRM.

7.9.5.11 I2C

The device contains six multicontroller Inter-Integrated Circuit (I2C) controllers. Each I2C controller was

designed to be compliant to the Philips I2C-bus™ specification version 2.1. However, the device IOs are not

fully compliant to the I2C electrical specification. The speeds supported and exceptions are described per port

below:

• MCU_I2C1, I2C1, I2C2, I2C3, I2C4, I2C5 and I2C6

– Speeds:

• Standard-mode (up to 100 Kbits/s)

– 1.8 V

– 3.3 V

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DRA821U-Q1

SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022

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