 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
DRA821U4...ALM 数据表(PDF) 184 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
DRA821U4...ALM 数据表(HTML) 184 Page - Texas Instruments |
|
|
184 / 252 page  • Fast-mode (up to 400 Kbits/s) – 1.8 V – 3.3 V – Exceptions: • The IOs associated with these ports are not compliant to the fall time requirements defined in the I2C specification because they are implemented with higher performance LVCMOS push-pull IOs that were designed to support other signal functions that could not be implemented with I2C compatible IOs. The LVCMOS IOs being used on these ports are connected such they emulate open-drain outputs. This emulation is achieved by forcing a constant low output and disabling the output buffer to enter the Hi-Z state. • The I2C specification defines a maximum input voltage VIH of (VDD max + 0.5 V), which exceeds the absolute maximum ratings for the device IOs. The system must be designed to ensure the I2C signals never exceed the limits defined in the Absolute Maximum Ratings section of this datasheet. • WAKEUP_I2C0, MCU_I2C0, and I2C0 – Speeds: • Standard-mode (up to 100 Kbits/s) – 1.8 V – 3.3 V • Fast-mode (up to 400 Kbits/s) – 1.8 V – 3.3 V • Hs-mode (up to 3.4 Mbit/s) – 1.8 V – Exceptions: • The IOs associated with these ports were not design to support Hs-mode while operating at 3.3 V. So Hs-mode is limited to 1.8-V operation. • The rise and fall times of the I2C signals connected to these ports must not exceed a slew rate of 0.8 V/ns (or 8E+7 V/s). This limit is more restrictive than the minimum fall time limits defined in the I2C specification. Therefore, it may be necessary to add additional capacitance to the I2C signals to slow the rise and fall times such that they do not exceed a slew rate of 0.8 V/ns. • The I2C specification defines a maximum input voltage VIH of (VDD max + 0.5 V), which exceeds the absolute maximum ratings for the device IOs. The system must be designed to ensure the I2C signals never exceed the limits defined in the Absolute Maximum Ratings section of this datasheet. Refer to the Philips I2C-bus specification version 2.1 for timing details. For more details about features and additional description information on the device Inter-Integrated Circuit, see the corresponding subsections within Signal Descriptions and Detailed Description sections. 7.9.5.12 I3C For more details about features and additional description information on the device Inter-Integrated Circuit, see the corresponding sections within Section 6.3, Signal Descriptions and Section 8, Detailed Description. Table 7-41, Table 7-42, Figure 7-75, Table 7-43, and Figure 7-76 assume testing over the recommended operating conditions and electrical characteristic conditions. Table 7-41. I3C Open Drain Timing Conditions PARAMETER MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate 0.2276 5 V/ns OUTPUT CONDITIONS CL Output load capacitance 50 pF DRA821U-Q1 SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022 www.ti.com 184 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DRA821U-Q1 |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
