DSP56362P datasheet(111/152 Pages) FREESCALE

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Power Consumption Considerations

DSP56362 Technical Data, Rev. 4

Freescale Semiconductor

5-3

•

Consider all device loads as well as parasitic capacitance due to PCB traces when calculating

capacitance. This is especially critical in systems with higher capacitive loads that could create

higher transient currents in the VCC and GND circuits.

•

All inputs must be terminated (i.e., not allowed to float) using CMOS levels, except for the pins

with internal pull-up resistors (TRST, TMS, DE, TCK, and TDI).

•

Take special care to minimize noise levels on the VCCP, GNDP, and GNDP1 pins.

•

If multiple DSP56362 devices are on the same board, check for cross-talk or excessive spikes on

the supplies due to synchronous operation of the devices.

•

RESET must be asserted when the chip is powered up. A stable EXTAL signal should be supplied

before deassertion of RESET.

•

At power-up, ensure that the voltage difference between the 5 V tolerant pins and the chip VCC

never exceeds 3.95 V.

5.3

Power Consumption Considerations

Power dissipation is a key issue in portable DSP applications. Some of the factors which affect current

consumption are described in this section. Most of the current consumed by CMOS devices is alternating

current (ac), which is charging and discharging the capacitances of the pins and internal nodes.

Current consumption is described by the following formula:

where:

= node/pin capacitance

= voltage swing

= frequency of node/pin toggle

The maximum internal current (ICCImax) value reflects the typical possible switching of the internal buses

on best-case operation conditions, which is not necessarily a real application case. The typical internal

current (ICCItyp) value reflects the average switching of the internal buses on typical operating conditions.

For applications that require very low current consumption, do the following:

•

Set the EBD bit when not accessing external memory.

•

Minimize external memory accesses and use internal memory accesses.

•

Minimize the number of pins that are switching.

•

Minimize the capacitive load on the pins.

•

Connect the unused inputs to pull-up or pull-down resistors.

Example 1. Current Consumption

For a Port A address pin loaded with 50 pF capacitance, operating at 3.3 V, and with a 100 MHz clock, toggling

at its maximum possible rate (50 MHz), the current consumption is

IC V

I50 10

–

3.3

50 10

8.25mA

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