DSP56362P datasheet(114/152 Pages) FREESCALE

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Host Port Considerations

DSP56362 Technical Data, Rev. 4

5-6

Freescale Semiconductor

significance, the host could read the wrong combination. Therefore, read the bits twice and

check for consensus.

•

Overwriting the Host Vector

—The host interface programmer should change the host vector

(HV) register only when the host command (HC) bit is clear. This ensures that the DSP interrupt

control logic will receive a stable vector.

•

Cancelling a Pending Host Command Exception

—The host processor may elect to clear the HC

bit to cancel the host command exception request at any time before it is recognized by the DSP.

Because the host does not know exactly when the exception will be recognized (due to exception

processing synchronization and pipeline delays), the DSP may execute the host command

exception after the HC bit is cleared. For these reasons, the HV bits must not be changed at the

same time that the HC bit is cleared.

•

Variance in the Host Interface Timing

—The host interface (HDI) may vary (e.g. due to the PLL

lock time at reset). Therefore, a host which attempts to load (bootstrap) the DSP should first make

sure that the part has completed its HI port programming (e.g., by setting the INIT bit in ICR then

polling it and waiting it to be cleared, then reading the ISR or by writing the TREQ/RREQ together

with the INIT and then polling INIT, ISR, and the HOREQ pin).

5.5.2

DSP Programming Considerations

•

Synchronization of Status Bits from Host to DSP

—DMA, HF1, HF0, HCP, HTDE, and HRDF

status bits are set or cleared by the host processor side of the interface. These bits are individually

synchronized to the DSP clock. (Refer to the user’s manual for descriptions of these status bits.)

•

Reading HF0 and HF1 as an Encoded Pair

—Care must be exercised when reading status bits

HF0 and HF1 as an encoded pair, (i.e., the four combinations 00, 01, 10, and 11 each have

significance). A very small probability exists that the DSP will read the status bits synchronized

during transition. Therefore, HF0 and HF1 should be read twice and checked for consensus.

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