DSP56362P datasheet(112/152 Pages) FREESCALE

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PLL Performance Issues

DSP56362 Technical Data, Rev. 4

5-4

Freescale Semiconductor

•

Disable unused peripherals.

•

Disable unused pin activity (e.g., CLKOUT, XTAL).

One way to evaluate power consumption is to use a current per MIPS measurement methodology to

minimize specific board effects (i.e., to compensate for measured board current not caused by the DSP).

A benchmark power consumption test algorithm is listed in Appendix A. Use the test algorithm, specific

test current measurements, and the following equation to derive the current per MIPS value.

where :

ItypF2 = current at F2

ItypF1 = current at F1

= high frequency (any specified operating frequency)

= low frequency (any specified operating frequency lower than F2)

NOTE

F1 should be significantly less than F2. For example, F2 could be 66 MHz

and F1 could be 33 MHz. The degree of difference between F1 and F2

determines the amount of precision with which the current rating can be

determined for an application.

5.4

PLL Performance Issues

The following explanations should be considered as general observations on expected PLL behavior.

There is no testing that verifies these exact numbers. These observations were measured on a limited

number of parts and were not verified over the entire temperature and voltage ranges.

5.4.1

Phase Skew Performance

The phase skew of the PLL is defined as the time difference between the falling edges of EXTAL and

CLKOUT for a given capacitive load on CLKOUT, over the entire process, temperature, and voltage

ranges. As defined in Figure 3-1, for input frequencies greater than 15 MHz and the MF

≤ 4, this skew is

greater than or equal to 0.0 ns and less than 1.8 ns; otherwise, this skew is not guaranteed. However, for

MF < 10 and input frequencies greater than 10 MHz, this skew is between

−1.4 ns and +3.2 ns.

5.4.2

Phase Jitter Performance

The phase jitter of the PLL is defined as the variations in the skew between the falling edges of EXTAL

and CLKOUT for a given device in specific temperature, voltage, input frequency, MF, and capacitive load

on CLKOUT. These variations are a result of the PLL locking mechanism. For input frequencies greater

than 15 MHz and MF

≤ 4, this jitter is less than ±0.6 ns; otherwise, this jitter is not guaranteed. However,

for MF < 10 and input frequencies greater than 10 MHz, this jitter is less than

±2 ns.

1MIPS

1MHz

(

typF2

ItypF1)

F2 F1

–

()

–

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